USB333X datasheet(11/85 Pages) MICROCHIP

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DS00001880A-page 11

USB333x

TABLE 2-2:

USB3330 PIN DESCRIPTION

Ball

Name

Direction/

Type

Active

Level

Description

Input,

Analog

N/A

For device applications the ID pin is connected to

VDD33

. For Host applications ID is grounded. For

OTG applications the ID pin is connected to the USB

connector.

VBUS

I/O,

Analog

N/A

This pin is used for the VBUS comparator inputs and

for VBUS pulsing during session request protocol. An

external resistor, RVBUS, is required between this pin

and the USB connector.

VBAT

Power

N/A

Regulator input. The regulator supply can be from

5.5V to 3.0V.

VDD33

Power

N/A

3.3V Regulator Output. A 1.0uF (<1 ohm ESR) bypass

capacitor to ground is required for regulator stability.

The bypass capacitor should be placed as close as

possible to the USB333x.

I/O,

Analog

N/A

D- pin of the USB cable.

I/O,

Analog

N/A

D+ pin of the USB cable.

REF[0]

I/O,

Digital 3.3V

N/A

Used to select REFCLK frequency. Connect to ground

or VDD33. Refer to Table 5-1 for frequency selection

options.

REF[1]

I/O,

Digital 3.3V

N/A

Used to select REFCLK frequency. Connect to ground

or VDD33. Refer to Table 5-1 for frequency selection

options.

DATA[7]

I/O,

CMOS

N/A

ULPI bi-directional data bus. DATA[7] is the MSB.

DATA[6]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

DATA[5]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

DATA[4]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

CLKOUT

Output,

CMOS

N/A

ULPI Clock Out Mode:

60MHz ULPI clock output. All ULPI signals are driven

synchronous to the rising edge of this clock.

ULPI Clock In Mode:

Connect this pin to VDD18 to configure 60MHz ULPI

Clock IN mode as described in Section 5.4.1.

DATA[3]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

DATA[2]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

DATA[1]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

DATA[0]

I/O,

CMOS

N/A

ULPI bi-directional data bus. DATA[0] is the LSB.

NXT

Output,

CMOS

High

The PHY asserts NXT to throttle the data. When the

Link is sending data to the PHY, NXT indicates when

the current byte has been accepted by the PHY.

DIR

Output,

CMOS

N/A

Controls the direction of the data bus. When the PHY

has data to transfer to the Link, it drives DIR high to

take ownership of the bus. When the PHY has no data

to transfer it drives DIR low and monitors the bus for

commands from the Link.

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