USB333X datasheet(26/85 Pages) MICROCHIP

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USB333x

DS00001880A-page 26

 2009 - 2015 Microchip Technology Inc.

Note 1:

This is equivalent to Table 40, Section 4.4 of the ULPI 1.1 specification.

USB333x does not support operation as an upstream hub port. See Section 6.4.1.3, "UTMI+ Level 3".

Note 5-1

When RESETB = 0 The HS termination will tri-state the USB drivers.

Note 5-2

The transceiver operation is not ensured in a combination that is not defined.

The USB333x uses the 27% resistor ECN resistor tolerances. The resistor values are shown in Table 4-6.

5.3

Bias Generator

This block consists of an internal bandgap reference circuit used for generating the driver current and the biasing of the

analog circuits. This block requires an external 8.06K

Ω, 1% tolerance, reference resistor connected from RBIAS to

ground. This resistor should be placed as close as possible to the USB333x to minimize the trace length. The nominal

voltage at RBIAS is 0.8V +/- 10% and therefore the resistor will dissipate approximately 80

μW of power.

5.4

Integrated Low Jitter PLL

The USB333x uses an integrated low jitter phase locked loop (PLL) to provide a clean 480MHz clock required for HS

USB signal quality. This clock is used by the PHY during both transmit and receive. The USB333x PLL requires an accu-

rate frequency reference to be driven on the REFCLK pin.

5.4.1

REFCLK FREQUENCY SELECTION

The USB333x PLL is designed to operate in one of two reference clock modes. In the first mode, the 60MHz ULPI clock

is driven on the REFCLK pin. In the second mode a reference clock is driven on the REFCLK pin. The Link is driving

the ULPI clock, in the first mode, and this is referred to as ULPI Clock In Mode. In the second mode, the USB333x

generates the ULPI clock, and this is referred to as ULPI Clock Out Mode.

During start-up, the USB333x monitors the CLKOUT pin. If a connection to VDD18 (USB3330, USB3331, USB3336,

and USB3338) or VDDIO (USB3333) is detected, the USB333x is configured for a 60MHz ULPI reference clock driven

on the REFCLK pin. Section 5.4.1.2 and Section 5.4.1.1 describe how to configure the USB333x for either ULPI Clock

In Mode or ULPI Clock Out Mode.

For the USB3331, USB3336, and USB3338, the reference clock frequency required is shown on the Product Identifica-

tion System page.

For the USB3330 and USB3333, the reference clock frequency required is determined by the settings of the REF

pins(s). The pins should either be connected to VDD33 or GND. The reference frequency selection options are shown

in Table 5-2 and Table 5-3.

OTG device, Peripheral FS

01b

00b

OTG device, Peripheral HS/FS Suspend

01b

00b

OTG device, Peripheral HS/FS Resume

01b

10b

OTG device, Peripheral Test J/Test K

00b

10b

Charger Detection

Connect Detect

01b

00b

Any combination not defined above, Note 5-

TABLE 5-1:

DP/DM TERMINATION VS. SIGNALING MODE (CONTINUED)

Signaling Mode

ULPI Register Settings

USB333x Termination

Resistor Settings

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