| поискавой системы для электроныых деталей |
|
USB333X датащи(PDF) 42 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
USB333X датащи(HTML) 42 Page - Microchip Technology |
|
42 / 85 page ![]() USB333x DS00001880A-page 42 2009 - 2015 Microchip Technology Inc. 6.1.2 ULPI INTERFACE TIMING IN SYNCHRONOUS MODE The control and data timing relationships are given in Figure 6-2 and Table 4-4. All timing is relative to the rising clock edge of the 60MHz ULPI Clock. 6.2 ULPI Register Access The following section details the steps required to access registers through the ULPI interface. At any time DIR is low the Link may access the ULPI registers set using the Transmit Command byte. The ULPI registers retain their contents when the PHY is in Low Power Mode, Full Speed/Low Speed Serial Mode, or Carkit Mode. 6.2.1 TRANSMIT COMMAND BYTE (TX CMD) A command from the Link begins a ULPI transfer from the Link to the USB333x. Before reading a ULPI register, the Link must wait until DIR is low, and then send a Transmit Command Byte (TX CMD) byte. The TX CMD byte informs the USB333x of the type of data being sent. The TX CMD is followed by a data transfer to or from the USB333x. Table 6-2 gives the TX command byte (TX CMD) encoding for the USB333x. The upper two bits of the TX CMD instruct the PHY as to what type of packet the Link is transmitting. FIGURE 6-2: ULPI SINGLE DATA RATE TIMING DIAGRAM IN SYNCHRONOUS MODE TABLE 6-2: ULPI TX CMD BYTE ENCODING Command Name CMD Bits[7:6] CMD Bits[5:0] Command Description Idle 00b 000000b ULPI Idle Transmit 01b 000000b USB Transmit Packet with No Packet Identifier (NOPID) 00XXXXb USB Transmit Packet Identifier (PID) where DATA[3:0] is equal to the 4-bit PID. P3P2P1P0 where P3 is the MSB. Register Write 10b XXXXXXb Immediate Register Write Command where: DATA[5:0] = 6-bit register address 101111b Extended Register Write Command where the 8-bit register address is available on the next cycle. Register Read 11b XXXXXXb Immediate Register Read Command where: DATA[5:0] = 6-bit register address 101111b Extended Register Read Command where the 8-bit register address is available on the next cycle. 60MHz ULPI - CLK Control In - STP Data In - DATA[7:0] Control Out - DIR, NXT Data Out - DATA[7:0] TSC TSD THC THD TDC TDC TDD |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |