USB333X datasheet(29/85 Pages) MICROCHIP

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DS00001880A-page 29

USB333x

5.4.3

REFCLK JITTER

The USB333x is tolerant to jitter on the reference clock. The REFCLK jitter should be limited to a peak to peak jitter of

less than 1nS over a 10uS time interval. If this level of jitter is exceeded when configured for either ULPI Clock Input

Mode or ULPI Clock Output Mode, the USB333x High Speed eye diagram may be degraded.

The frequency accuracy of the REFCLK must meet the +/- 500ppm requirement as shown in Table 4-3.

5.4.4

REFCLK ENABLE/DISABLE

The REFCLK should be enabled when the RESETB pin is brought high. The ULPI interface will start running after the

time specified in Table 4-3. If the reference clock enable is delayed relative to the RESETB pin, the ULPI interface will

start operation delayed by the same amount. The reference clock can be run at anytime the RESETB pin is low without

causing the USB333x to start-up or draw current.

When the USB333x is placed in Low Power Mode or Carkit Mode, the reference clock can be stopped after the final

ULPI register write is complete. The STP pin is asserted to bring the USB333x out of Low Power Mode. The reference

clock should be started at the same time STP is asserted to minimize the USB333x start-up time.

If the reference clock is stopped while in ULPI Synchronous mode the PLL will come out of lock and the frequency of

oscillation will decrease to the minimum allowed by the PLL design. If the reference clock is stopped during a USB ses-

sion, the session may drop.

5.5

Internal Regulators and POR

The USB333x includes integrated power management functions, including a Low-Dropout regulator that can be used

to generate the 3.3V USB supply, an integrated 1.8V regulator, and a POR generator described in Section 5.5.2.

5.5.1

INTEGRATED LOW DROPOUT REGULATORS

The USB333x includes two integrated linear regulators. Power sourced at the VBAT pin is regulated to 3.3V and 1.8V

output on the VDD33 and VDD18 pins. To ensure stability, both regulators require an external bypass capacitor as spec-

ified in Table 4-12 placed as close to the pins as possible. VBAT and VDD33 should never be shorted together.

The USB333x regulators are designed to generate the 3.3 Volt and 1.8 Volt supplies for the USB333x only. Using the

regulators to provide current for other circuits is not recommended and Microchip does not guarantee USB performance

or regulator stability.

During USB UART mode the 3.3V regulator output voltage can be changed to allow the USB333x to work with UARTs

operating at different operating voltages. The 3.3V regulator output is configured to the voltages shown in Table 4-12

with the UART RegOutput[1:0] bits in the USB IO & Power Management register.

The regulators are enabled by the RESETB pin. When RESETB pin is low both regulators are disabled and the regulator

outputs are pulled low by weak pull-down. The RESETB pin must be brought high to enable the regulators.

For peripheral-only or host-only bus-powered applications, the VBAT supply shown below in Figure 5-7 may be con-

nected to the VBUS pin of the USB connector for bus powered applications. In this configuration, external overvoltage

protection is required to protect the VBAT supply from any transient voltage present at the VBUS pin of the USB con-

nector. Additionally, the VBAT input must never be exposed to a voltage that exceeds VVBAT. (See Table 3-2.)

Also in this configuration, the VBUS line must never be connected to a system utilizing a +30V VBUS level (i.e. Some

USB battery chargers). Microchip does not recommend connecting the VBAT pin directly to the VBUS terminal of the

USB connector.

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