USB333X datasheet(40/85 Pages) MICROCHIP

40 / 85 page

USB333x

DS00001880A-page 40

 2009 - 2015 Microchip Technology Inc.

6.0

ULPI OPERATION

6.1

ULPI Introduction

The USB333x uses the industry standard ULPI digital interface for communication between the transceiver and Link

(device controller). The ULPI interface is designed to reduce the number of pins required to connect a discrete USB

transceiver to an ASIC or digital controller. For example, a full UTMI+ Level 3 OTG interface requires 54 signals while

a ULPI interface requires only 12 signals.

The ULPI interface is documented completely in the “UTMI+ Low Pin Interface (ULPI) Specification Revision 1.1”. The

following sections describe the operating modes of the USB333x digital interface.

Figure 6-1 illustrates the block diagram of the ULPI digital functions. It should be noted that this USB333x does not use

a “ULPI wrapper” around a UTMI+ PHY core as the ULPI specification implies.

The advantage of a “wrapper-less” architecture is that the USB333x has a lower USB latency than a design which must

first register signals into the PHY’s wrapper before the transfer to the transceiver core. A low latency PHY allows a wrap-

per around a UTMI Link to be used and still make the required USB turn-around timing required by the USB 2.0 speci-

fication.

FIGURE 6-1:

ULPI DIGITAL BLOCK DIAGRAM

NOTE:

The ULPI interface

is a wrapperless

design.

POR

ULPI Register Array

Interrupt Control

Data[7:0]

High Speed TX

Full Speed TX

Low Speed TX

High Speed Data

Recovery

Full / Low Speed

Data Recovery

ULPI Protocol

Block

HS Tx Data

FS/LS Tx Data

HS RX Data

FS/LS Data

DIR

NXT

STP

Tx Data

Rx Data

USB Transmit and Receive Logic

RESETB

Rid State

Machine

To RX

Analog

To TX

Analog

OTG

Analog

To USB

Audio

Analog

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