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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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USB333X датащи(PDF) 27 Page - Microchip Technology |
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USB333X датащи(HTML) 27 Page - Microchip Technology |
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27 / 85 page  2009 - 2015 Microchip Technology Inc. DS00001880A-page 27 USB333x 5.4.1.1 ULPI Clock Output Mode When using ULPI Clock Output Mode, the USB333x generates the 60MHz ULPI clock used by the Link. In this mode, the REFCLK pin must be driven with the model-specific frequency, and the CLKOUT pin sources the 60MHz ULPI clock to the Link. When using ULPI Clock Output Mode, the system must not drive the CLKOUT pin following POR or hard- ware reset with a voltage that exceeds the value of VIH_ED provided in Table 4-4. An example of ULPI Clock Out Mode is shown in Figure 8-1 After the PLL has locked to the correct frequency, the USB333x generates the 60MHz ULPI clock on the CLKOUT pin, and de-asserts DIR to indicate that the PLL is locked. The USB333x is set to start the clock within the time specified in Table 4-3, and it will be accurate to within ±500ppm. For Host applications the ULPI AutoResume bit should be enabled. This is described in Section 6.4.1.4. When using ULPI Clock Output Mode, the edges of the reference clock do not need to be aligned in any way to the ULPI interface signals. There is no need to align the phase of the REFCLK and the CLKOUT. TABLE 5-2: REF[1:0] VS. REQUIRED FREQUENCY AT REFCLK (USB3330) REF[1:0] REFCLK Frequency 00 19.2 MHz 01 26 MHz 10 13 MHz 11 24 MHz TABLE 5-3: REF[0] VS. REQUIRED FREQUENCY AT REFCLK (USB3333) REF[0] REFCLK Frequency 0 19.2 MHz 126 MHz FIGURE 5-4: CONFIGURING THE USB333X FOR ULPI CLOCK OUTPUT MODE CLKOUT REFCLK PHY From PLL Clock Source To PLL Link ULPI Clk In |
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