XRT75VL00D datasheet(83/92 Pages) EXAR

83 / 92 page

XRT75VL00D

REV. 1.0.3

E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

• If the LIU has been configured to operate in the Hardware Mode

Then the user should tie the (SR/DR*) pin to "High".

Configure each of the channels within the LIU to operate in the SONET De-Sync Mode

The user can accomplish this by executing either of the following steps.

• If the LIU has been configured to operate in the Host Mode.

Then the user should set Bit D2 (JA0) to "0" and Bit D0 (JA1) to "1", within the Jitter Attenuator Control

• If the LIU has been configured to operate in the Hardware Mode

Then the user should tie pin 44 (JA0) to a logic "HIGH" and pin 42 (JA1) to a logic "LOW".

Once the user accomplishes either of these steps, then the Jitter Attenuator (within the LIU) will be configured

to operate with a very narrow bandwidth.

Configure the Jitter Attenuator (within each of the channels) to operate in the Transmit Direction.

The user can accomplish this by executing either the following steps.

• If the LIU has been configured to operate in the Host Mode.

Then the user should be Bit D1 (JATx/JARx*) to "1", within the Jitter Attenuator Control Register, as depicted

below.

CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06

CHANNEL 1 ADDRESS LOCATION = 0X0E

CHANNEL 2 ADDRESS LOCATION = 0X16

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1

BIT 0

Unused

PRBS Enable

Ch_n

RLB_n

LLB_n

E3_n

STS-1/

DS3_n

SR/DR_n

R/O

R/W

0000

JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07

CHANNEL 1 ADDRESS LOCATION = 0X0F

CHANNEL 2 ADDRESS LOCATION = 0X17

BIT 7BIT 6BIT 5BIT 4BIT 3

BIT 2BIT 1

BIT 0

Unused

SONET APS

Recovery

Time

DisableCh_n

JA RESET

Ch_n

JA1 Ch_n

JA in Tx Path

Ch_n

JA0 Ch_n

R/O

R/W

0000

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