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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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XRT75VL00D датащи(PDF) 49 Page - Exar Corporation |
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XRT75VL00D датащи(HTML) 49 Page - Exar Corporation |
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49 / 92 page  XRT75VL00D REV. 1.0.3 E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 44 XRT75VL00D can be configured in Analog Loopback either in Hardware mode via the LLB and RLB pins or in Host mode via LLB and RLB bits in the channel control registers. NOTES: 1. In the Analog loopback mode, data is also output via TTIP and TRING pins. 2. Signals on the RTIP and RRING pins are ignored during analog loopback. 8.2.2 DIGITAL LOOPBACK: The Digital Loopback function is available either in Hardware mode or Host mode. When the Digital Loopback is selected, the transmit clock (TxClk) and transmit data inputs (TPDATA & TNDATA) are looped back and output onto the RxClk, RPOS and RNEG pins as shown in Figure 27. The data presented on TxClk, TPDATA and TNDATA are not output on the TTIP and TRING pins.This provides the capability to configure the protection card (in redundancy applications) in Digital Loopback mode without affecting the traffic on the primary card. NOTE: Signals on the RTIP and RRING pins are ignored during digital loopback. FIGURE 26. ANALOG LOOPBACK TRING TTIP RRING RTIP RPOS RNEG RCLK TNDATA TCLK TPDATA HDB3/B3ZS1 ENCODER HDB3/B3ZS1 DECODER TIMING CONTROL DATA & CLOCK RECOVERY 1 if enabled 2 if enabled and selected in either Receive or Transmit path Tx Rx |
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