XRT75VL00D datasheet(32/92 Pages) EXAR

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XRT75VL00D

E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

REV. 1.0.3

When the MTIP and MRing are connected to the TTIP and TRing lines, the drive monitor circuit monitors the

line for transitions. The DMO (Drive Monitor Output) will be asserted “Low” as long as the transitions on the line

are detected via MTIP and MRing.

If no transitions on the line are detected for 128 ± 32 TxClk periods, the DMO output toggles “High” and when

the transitions are detected again, DMO toggles “Low”.

NOTE: The Drive Monitor Circuit is only for diagnostic purposes and does not have to be used to operate the transmitter.

4.5

Transmitter Section On/Off:

The transmitter section can be turned on or off. To turn on the transmitter in the Hardware mode, pull TxON pin

“High”. In the Host mode, write a “1” to the TxON control bit AND pull the TxON pin “High” to turn on the

transmitter.

When the transmitter is turned off, the TTIP and TRing are tri-stated.

NOTES:

This feature provides support for Redundancy.

If the XRT75VL00D is configured in Host mode, to permit a system designed for redundancy to quickly shut-off

the defective line card and turn on the back-up line card, writing a “1” to the TxON control bit transfers the control

to TxON pin.

5.0

THE RECEIVER SECTION:

This section describes the detailed operation of the various blocks in the receiver. The receiver recovers the

TTL/CMOS level data from the incoming bipolar B3ZS or HDB3 encoded input pulses.

5.1

AGC/Equalizer:

The Adaptive Gain Control circuit amplifies the incoming analog signal and compensates for the various flat

losses and also for the loss at one-half symbol rate. The AGC has a dynamic range of 30 dB.

The Equalizer restores the integrity of the signal and compensates for the frequency dependent attenuation of

up to 900 feet of coaxial cable (1300 feet for E3). The Equalizer also boosts the high frequency content of the

signal to reduce the Inter-Symbol Interference (ISI) so that, the slicer slices the signal at 50% of peak voltage to

generate Positive and Negative data.

The Equalizer can either be “IN” or “OUT” by setting the REQEN pin “High” or “Low” (in Hardware Mode) or

setting the REQEN control bit to “1” or “0” (in Host Mode).

RECOMMENDATIONS FOR EQUALIZER SETTINGS:

The Equalizer has two gain settings to provide optimum equalization. In the case of normally shaped DS3/

STS-1 pulses (pulses that meet the template requirements) that has been driven through 0 to 900 feet of cable,

the Equalizer can be left “IN” by setting the REQEN pin to “High” (in Hardware Mode) or setting the REQEN

control bit to “1” (in Host Mode).

However, for square-shaped pulses such as E3 or for DS3/STS-1 high pulses (that does not meet the pulse

template requirements), it is recommended that the Equalizer be left “OUT” for cable length less than 300 feet

by setting the REQEN pin “Low” (in Hardware Mode) or by setting the REQEN control bit to “0” (in Host

Mode).This would help to prevent over-equalization of the signal and thus optimize the performance in terms of

better jitter transfer characteristics.

NOTE: The results of extensive testing indicates that even when the Equalizer was left “IN” (REQEN = “HIGH”), regardless

of the cable length, the integrity of the E3 signal was restored properly over 0 to 12 dB cable loss at Industrial

Temperature.

The Equalizer also contain an additional 20 dB gain stage to provide the line monitoring capability of the

resistively attenuated signals which may have 20dB flat loss. This capability can be turned on by writing a “1” to

the RxMON bits in the control register or by setting the RxMON pin (pin 27) “High”.

5.1.1

Interference Tolerance:

For E3 mode, ITU-T G.703 Recommendation specifies that the receiver be able to recover error-free clock and

data in the presence of a sinusoidal interfering tone signal. For DS3 and STS-1 modes, the same

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