XRT75VL00D datasheet(34/92 Pages) EXAR

34 / 92 page

XRT75VL00D

E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

REV. 1.0.3

5.2

Clock and Data Recovery:

The Clock and Data Recovery Circuit extracts the embedded clock, from the sliced digital data stream and

provides the retimed data to the B3ZS (HDB3) decoder.

The Clock Recovery PLL can be in one of the following two modes:

TRAINING MODE:

In the absence of input signals at RTIP and RRing pins, or when the frequency difference between the

recovered line clock signal and the reference clock applied on the ExClk input pin exceed 0.5%, the clock

recovery unit enters into Training Mode and a Loss of Lock condition is declared by toggling RLOL output pin

“High” (in Hardware Mode) or setting the RLOL bit to “1” in the control registers (in Host Mode). Also, the clock

output on the RxClk pin is the same as the reference clock applied on ExClk pin.

DATA/CLOCK RECOVERY MODE:

In the presence of input line signals on the RTIP and RRing input pins and when the frequency difference

between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on

the RxClk out pin is the Recovered Clock signal.

5.3

B3ZS/HDB3 Decoder:

The decoder block takes the output from clock and data recovery block and decodes the B3ZS (for DS3 or

STS-1) or HDB3 (for E3) encoded line signal and detects any coding errors or excessive zeros in the data

stream.

Whenever the input signal violates the B3ZS or HDB3 coding sequence for bipolar violation or contains three

(for B3ZS) or four (for HDB3) or more consecutive zeros, an active “High” pulse is generated on the RLCV

output pins to indicate line code violation.

NOTE: In Single- Rail (NRZ) mode, the decoder is bypassed.

5.4

LOS (Loss of Signal) Detector:

5.4.1

DS3/STS-1 LOS Condition:

A Digital Loss of Signal (DLOS) condition occurs when a string of 175 ± 75 consecutive zeros occur on the line.

When the DLOS condition occurs, the DLOS bit is set to “1” in the status control register. DLOS condition is

cleared when the detected average pulse density is greater than 33% for 175 ± 75 pulses.

Analog Loss of Signal (ALOS) condition occurs when the amplitude of the incoming line signal is below the

threshold as shown in the Table 10.The status of the ALOS condition is reflected in the ALOS status control

RLOS is the logical OR of the DLOS and ALOS states. When the RLOS condition occurs the RLOS output pin

is toggled “High” and the RLOS bit is set to “1” in the status control register.

TABLE 9: INTERFERENCE MARGIN TEST RESULTS

MODE

CABLE LENGTH (ATTENUATION)INTERFERENCE TOLERANCE

0 dB

-14 dB

12 dB

-18 dB

DS3

0 feet

-17 dB

225 feet

-16 dB

450 feet

-16 dB

STS-1

0 feet

-16 dB

225 feet

-15 dB

450 feet

-15 dB

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