XRT75VL00D datasheet(2/92 Pages) EXAR

2 / 92 page

XRT75VL00D

E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

REV. 1.0.3

TRANSMIT INTERFACE CHARACTERISTICS

• Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the

line

• Integrated Pulse Shaping Circuit.

• Built-in B3ZS/HDB3 Encoder (which can be disabled).

• Accepts Transmit Clock with duty cycle of 30%-70%.

• Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications.

• Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and

ANSI T1.102_1993.

• Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253-CORE.

• Transmitter can be turned off in order to support redundancy designs.

RECEIVE INTERFACE CHARACTERISTICS

• Integrated Adaptive Receive Equalization for optimal Clock and Data Recovery.

• Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications.

• Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications.

• Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications.

• Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms.

• Built-in B3ZS/HDB3 Decoder (which can be disabled).

• Recovered Data can be muted while the LOS Condition is declared.

FIGURE 1. BLOCK DIAGRAM OF THE XRT 75VL00D

HOST/HW

STS-1/DS3

REQEN

RTIP

RRING

SR/DR

XRT75L03

RLB

RLOS

JATx/Rx

TPData

TNData

TxClk

TAOS

TxLEV

TxON

Note: Serial Processor Interface input pins are shared by in "Host" Mode and redefined in the "Hardware" Mode.

Device

Monitor

MTIP

MRING

DMO

Timing

Control

TTIP

TRING

Pulse

Shaping

HDB3/

B3ZS

Encoder

RLOL

RxON

RxClkINV

RxClk

RPOS

RNEG/

LCV

Control

Jitter

Attenuator

MUX

Line

Driver

LLB

Invert

Remote

LoopBack

HDB3/

B3ZS

Decoder

MUX

AGC/

Equalizer

Peak Detector

LOS

Detector

Slicer

Jitter

Attenuator

Serial

Processor

Interface

Local

LoopBack

Clock & Data

Recovery

Clock

Synthesizer

ExClk/12M

RESET

SClk

INT

SDO

SDI

CLK_OUT

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