XRT75VL00D datasheet(44/92 Pages) EXAR

44 / 92 page

XRT75VL00D

E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

REV. 1.0.3

0x03

Read

Only

DMO

This bit is set to “1” every time the MTIP/MRing input

pins have not detected any bipolar pulses for 128

consecutive bit periods.

RLOS

This bit is set to “1” every time the receiver declares

an LOS condition.

RLOL

This bit is set to “1” every time when the receiver

declares a Loss of Lock condition.

This bit is set to “1” every time the FIFO in the Jitter

Attenuator is within 2 bit of underflow/overflow condi-

tion.

ALOS

This bit is set to “1” every time the receiver declares

Analog LOS condition.

DLOS

This bit is set to “1” every time the receiver declares

Digital LOS condition.

PRBSLS

This bit is set to “1” every time the PRBS detects a bit

error.

0x04

R/W

TxLEV

Writing a “1” to this bit disables the Transmit Build-out

circuit and writing a “0” enables the Transmit Build-out

circuit.

NOTE: See section 4.03 for detailed description.

TxClkINV

Writing a “1” to this bit configures the transmitter to

sample the data on TPData/TNData input pins on the

rising edge of TxClk.

TAOS

Setting this bit to “1” causes a continuous stream of

marks to be sent out at the TTIP and TRing pins.

Reserved

This Bit Location is Not Used.

INSPRBS

Writing a “1” to this bit causes the PRBS generator to

insert a single-bit error onto the transmit PRBS data

stream.

NOTE: PRBS Generator/Detector must be enabled

for this bit to have any effect.

TxMON

When this bit is set to “1”, the driver monitor is con-

nected to its own transmit channel and monitors the

transmit driver. When a transmit failure is detected,

the DMO output will go high.

When this bit is “0”, MTIP and MRing can be con-

nected to other transmit channel for monitoring.

TABLE 16: REGISTER MAP DESCRIPTION

ADDRESS

(HEX)

TYPE

BIT LOCATION

SYMBOL

DESCRIPTION

DEFAULT

VALUE(BIN)

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