IP4856CX25_C

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Product data sheet

Rev. 2 — 15 October 2014

12 of 21

NXP Semiconductors

IP4856CX25/C

SD 3.0-compliant memory card integrated dual voltage level translator

12.2 Level translator

[1]

[2]

Table 12.

Level translator dynamic characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Host-side transition times

rise time

SEL = HIGH (1.8 V interface)

[1]

-0.4

1.0

ns

fall time

SEL = HIGH (1.8 V interface)

[1]

-0.4

1.0

ns

Card-side transition times

rise time

SEL = HIGH (1.8 V interface)

[2]

0.40.9

1.4ns

fall time

SEL = HIGH (1.8 V interface)

[2]

0.40.9

1.4ns

Host-side to card-side propagation delay

DATAx_H to DATAx_SD, CMD_H to CMD_SD and CLK_IN to CLK_SD

propagation delay

SEL = HIGH (1.8 V interface)

-

2.4

3.5

ns

Host-side to host-side propagation delay

CLK_IN to CLK_FB

propagation delay

SEL = HIGH (1.8 V interface)

-

4.8

7.0

ns

Card-side to host-side propagation delay

DATAx_SD to DATAx_H and CMD_SD to CMD_H

propagation delay

SEL = HIGH (1.8 V interface)

-

2.4

3.5

ns

Fig 6.

Output rise and fall times