IP4856CX25SLASHC datasheet(8/22 Pages) NEXPERIA

8 / 22 page

IP4856CX25_C

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 15 October 2014

7 of 21

NXP Semiconductors

IP4856CX25/C

SD 3.0-compliant memory card integrated dual voltage level translator

An external capacitor is needed between the regulator output pin VLDO and ground for

proper operation of the integrated voltage regulator. See Table 8 for recommended

capacitance and equivalent series resistance. To place the capacitor close to the VLDO pin

and maintain short connections to both, to the VLDO and to the ground, is recommended.

8.4 Memory card voltage tracking (reference select)

The device can track the memory card supply via pin VSD_REF. This allows achieving

optimum interoperability by perfectly matching input/output levels between voltage

translator and memory card in the 3 V signaling mode. Therefore, the voltage regulator

aims to follow the reference voltage provided at input VSD_REF directly. If tracking of the

memory card supply is not desired, connect pin VSD_REF to ground so the voltage

regulator refers to an integrated voltage reference. For 1.8 V (SEL = HIGH) signaling, the

voltage regulator is referred to the internal reference which is independent of the voltage

at VSD_REF.

8.5 Feedback clock channel

The clock is transmitted from the host to the memory card side. The voltage translator and

the Printed-Circuit Board (PCB) tracks introduce some amount of delay. It reduces timing

margin for data read back from memory card, especially at higher data rates. Therefore,

a feedback path is provided to compensate the delay. The reasoning behind this approach

is the fact that the clock is always delivered by the host, while the data in the timing critical

read mode comes from the card.

8.6 EMI filter

All input/output driver stages are equipped with EMI filters to reduce interferences towards

sensitive mobile communication.

8.7 ESD protection

The device has robust ESD protections on all memory card pins as well as on the VSD_REF

and VSUPPLY pins. The architecture prevents any stress for the host: the voltage translator

discharges any stress to supply ground.

Pins Write Protect (WP) and Card Detection (CD) might be pulled down by the memory

card which has to be detected by the host. Both signals must be HIGH if no card is

inserted. Therefore the pins are equipped with International Electrotechnical

Commission (IEC) system-level ESD protections and pull-up resistors connected to the

host supply VCCA.

IP4856CX25/C датащи(PDF) 8 Page - Nexperia B.V. All rights reserved