IP4856CX25_C

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© NXP Semiconductors N.V. 2014. All rights reserved.

Product data sheet

Rev. 2 — 15 October 2014

4 of 21

NXP Semiconductors

IP4856CX25/C

SD 3.0-compliant memory card integrated dual voltage level translator

7.

Pinning information

7.1 Pinning

7.2 Pin description

Fig 3.

Pin configuration WLCSP25

Table 2.

Pin allocation table

Pin

Symbol

Pin

Symbol

Pin

Symbol

Pin

Symbol

Pin

Symbol

A1

DATA2_H

A2

DIR_CMD

A3

DIR_0

A4

A5

DATA2_SD

B1

DATA3_H

B2

SEL

B3

B4

B5

DATA3_SD

C1

CLK_IN

C2

ENABLE

C3

GND

C4

C5

CLK_SD

D1

DATA0_H

D2

CMD_H

D3

CD

D4

CMD_SD

D5

DATA0_SD

E1

DATA1_H

E2

CLK_FB

E3

DIR_1_3

E4

WP

E5

DATA1_SD

aaa-015216

transparent top view,

solder balls facing down

D

B

E

C

A

24

135

bump A1

index area

Table 3.

Pin description

Pin

Description

DATA2_H

A1

I/O

data 2 input or output on host side

DIR_CMD

A2

I

direction control input for command

DIR_0

A3

I

direction control input for data 0

A4

S

supply voltage (from battery or regulator)

DATA2_SD

A5

I/O

data 2 input or output on memory card side

DATA3_H

B1

I/O

data 3 input or output on host side

SEL

B2

I

card side I/O voltage level select

B3

S

supply voltage from host side

B4

O

internal supply decoupling

DATA3_SD

B5

I/O

data 3 input or output on memory card side