STLC1510 datasheet(37/40 Pages) STMICROELECTRONICS

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STLC1510

8.4 AFE Interface

The interface to the companion Analog Front-end de-

vice (STLC1511) operates at a rate of 35.328MHz. It

consists of two types:

A serial signal interface for transferring DAC

and ADC samples to and from the Aloha ASIC

ASIC.

A serial control interface for Aloha ASIC.

The serial signal interface to the Aloha ASIC provides

for transport of transmit and receive data between

the LAVA ASIC and Aloha ASIC. This is accom-

plished with a two bit wide data stream in each direc-

tion plus the appropriate clocks. Refer to Figure 27.

for the timing diagram of this interface.

The serial signal interface consists of six pins:

A 35.328MHz continuous clock output

(CK35M);

A dual serial pin input pin for ADC samples

(RxSIN);

• It can carry up to 16 bits. The exact

number of bits carried is programmable

between 12 and 16. Refer to the AFE

interface definition for details.

A dual serial pin output pin for DAC samples

(TxSOUT);

It can carry up to 16 bits. The exact number of

bits carried is programmable between 14 and

16. Refer to the AFE interface definition for

details

An ADC and DAC sample clock input

(A_SCLK).

For TX and RX interface, data is sent on positive

edge of clock and sampled by the receiver on

the negative edge of the clock.

The serial control I/F consists of 4 pins:

SPI_CLK: a gated 35.328MHz clock.

It is only

present during digital I/F read/write cycles and is

inactive otherwise.

SPI_ENB: an active low enable pin which allows

selection between different AFEs if required.

SPI_DTX: an output data pin which is used to

send control information to the AFE ASIC.

SPI_DRX: an input data pin which is used

receive control information from the AFE ASIC.

It is enabled only when

R/W is low.

The format for the serial interface is given below:

R/W - determines the access mode for the

address[b1:b0].

ADDR[b2:b0] - identifies the control register

accessed. These registers will correspond to

the mapping in the LAVA ASIC.

WR_DATA[b7:b0] - the control data written to

the AFE ASIC.

Figure 27. AFE ADC/DAC Sample Serial Interface Timing Diagram

C K 35M

Tx S O U T [ 0 ]

Tx S O U T [ 1 ]

a1 5

a1 4

a1 3

a1 2

a11

a1 0

A _SC LK

b1 5

b1 4

b1 3

b1 2

b11

b10

RxS IN [ 0 ]

R x SIN [ 1]

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