STLC1510 datasheet(33/40 Pages) STMICROELECTRONICS

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STLC1510

Figure 20. Network Serial Interface Tx Timing

In the Rx direction, the most significant bit of a data

byte is transmitted to the network first, with the least

significant bit transmitted last. The serial data stream

is sampled by the network on the rising edge of Rx-

Clk. Samples at the gapped positions are ignored.

Figure 21. illustrates the Rx timing diagram of the se-

rial interface. Ignored samples are indicated by ’X’ in

the timing diagram.

8.2 UTOPIA Level 2 Interface

The Utopia Level 2 Interface is an 8-bit interface, op-

erating independently in the TX and RX directions.

The Utopia Level 2 Interface is briefly illustrated in

Figure 22.

General features:

Implemented according to The ATM Forum

Technical Committee’s Utopia Level 2

specification. Utopia Level 2 is an extension of

Utopia Level 1 which provides for connecting

multiple MPHY layer devices to a single ATM

layer. Once a given MPHY layer device has

been selected for data transfer according to the

mechanisms specified in Utopia Level 2, the

transfer itself is performed according to the

mechanisms specified in Utopia Level 1.

8-bit data transfer in each direction (TX and

RX), with a maximum clock speed of

approximately 21 MHz.

Clocks are provided by the ATM layer through

the TxClk and RxClk ports. (ATM layer is the

master, PHY layer is the slave)

There are 5 address lines for each of the TX and

RX interfaces. Up to 31 addresses are

supported, with the 32nd address (11111) being

a reserved, idle address. Single PHY operation

is supported by leaving the address lines set to

the address of the PHY device.

For more information, please see the ATM

Tx Clk

U T x Data[0 ] B(1 )

B(0 )

B(7 )

B( 6)

B (5)

B (4)

Figure 21. Network Serial Interface Rx Timing

Rx Clk

UR x D ata[0]

B(1 )

B(0 )

B(7 )

B(6 )

B(5 )

Figure 22. The NIF Utopia Level 2 Interface

S TLC 1510

Tx C lk

Rx Clk

U Tx Data[7:0]

U R x Da ta[7:0 ]

Ne tw o rk

Tx E n b

Tx S O C

Tx P a rity

R xA ddr[4 :0]

Rx Cla v

Tx Cla v

Tx BP

Rx En b

Tx A d d r[4 :0 ]

Rx S O C

Rx P a rity

(M PH Y

La y e r)

(ATM

La y e r)

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