STLC1510 datasheet(6/40 Pages) STMICROELECTRONICS

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STLC1510

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Test Interface

TCK

5V Tol CMOS input

JTAG Test Clock

TMS

5V Tol CMOS input

JTAG Test Mode Select

TDI

5V Tol CMOS input

JTAG Test Data Input

TDO

5V Tol 3.3V TTL 2mA slew ltd

output

JTAG Test Data Output

TRSTN

5V Tol CMOS input

dedicated TAP reset (active low)

Network Interface (UTOPIA / Serial Clock & Data)

TxClk

I/O

5V Tol CMOS input/ 5V Tol 3.3V

TTL 2mA slew ltd output

Input Utopia2 Tx clock or output PSIF

Tx clock.

TxClav

5V Tol 3.3V TTL 2mA slew ltd

output

Tx cell available signal.

TxBP

5V Tol 3.3V TTL 2mA slew ltd

output

Tx back pressure signal.

TxEnb

5V Tol. CMOS input

Tx Enable.

TxSOC

5V Tol CMOS input

Tx start of Cell

UTxData_7

5V Tol CMOS input

Utopia2 Transmit data bit 7

UTxData_6

5V Tol CMOS input

Utopia2 Transmit data bit 6

UTxData_5

5V Tol CMOS input

Utopia2 Transmit data bit 5

UTxData_4

5V Tol CMOS input

Utopia2 Transmit data bit 4

UTxData_3

5V Tol CMOS input

Utopia2 Transmit data bit 3

UTxData_2

5V Tol CMOS input

Utopia2 Transmit data bit 2

UTxData_1

5V Tol CMOS input

Utopia2 Transmit data bit 1

UTxData_0

5V Tol CMOS input

Utopia2 Transmit data bit 0; also CDIF

input data

TxAddr_4

5V Tol CMOS input

Utopia2 Transmit Address

TxAddr_3

5V Tol CMOS input

Utopia2 Transmit Address

TxAddr_2

5V Tol CMOS input

Utopia2 Transmit Address

TxAddr_1

5V Tol CMOS input

Utopia2 Transmit Address

TxAddr_0

5V Tol CMOS input

Utopia2 Transmit Address

TxParity

5V Tol. CMOS input

Odd parity bit of the data on

UTxData[7:0].

RxClk

I/O

5V Tol CMOS input/ 5V Tol 3.3V

TTL 2mA slew ltd output

Input Utopia2 Rx clock or output PSIF

Rx clock.

Table 2. Pad Description

Signal

I/O

Pad Type

Description

BGA

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