STLC1510 datasheet(17/40 Pages) STMICROELECTRONICS

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STLC1510

A status register, an index register (for the Host

Processor), an interrupt mask register, and a

message buffer are required for both input and

output transactions.

The Input Status Register (ISR) is set by the

Host Processor by writing h01 and cleared by

writing h00 to the location. It is cleared by ARM

by writing anything to it.

The Output Status Registers (OSR) is set by the

ARM by writing h01 and cleared by writing h00.

It is cleared by the Host Processor by writing

anything to it.

The Input and Output Index Registers (IIR &

OIR respectively) are reset to their starting

value by writing h00 to their respective

addresses. They can also be cleared by the

Host Processor by writing anything to them.

The Input Interrupt Mask Register (IIM) resets to

h00, causing the Mask to be set (active low).

This means that before the ARM can receive

message ready interrupts from the Host

Processor, this register must be written with

h0001 (by ARM) to unmask the interrupt.

The Output Interrupt Mask Register (OIM)

resets to h00, causing the Mask to be set (active

low). This means that before the Host Processor

can receive message ready interrupts from the

ARM, this register must be written with h01 (by

the Host Processor) to unmask the interrupt.

The Input and Output Message buffers are each

256 bytes long and 1 byte wide (an overflow in

the index register will not write to the other

message buffer, but will start to overwrite the

current message buffer).

Addressing of the Input and Output Message

Buffers by the Host Processor is implemented

indirectly via the Input and Output Index

Registers.

An external interrupt signal is generated when

the output status register is set by the ARM7. An

ARM7 interrupt signal is generated when the

input status register is set by the Host

Processor.

Figure 5. HPI Block Diagram

256 Bytes

HPI_CSN

HPI_RW N

H PI_A D D R [2:0]

H PI_D ATA_ IN [7:0]

HP I

AR M 2H P_ IN T

H P I2AR M_ IN T

PS EL _ H PI

PA DDR[1 0:1 ]

PD _W [7 :0]

PW R ITE

O utput Index R e g

Input Sta tus R eg

In pu t Index R eg

Input In t M ask

256 B ytes

Ou tput

Me ssa ge

Buffer

R ead/W rite

Rea d

R ead

R e ad /W rite

O u tput S tatus R e g

O utput Int M ask

HPI_A SN

BR ESn

HP I_DATA_O UT[7 :0 ]

HP I_DATA_O EN

BC L K

PE N AB L E

HPI_CL K

PD _R [1 5 :0]

To /F ro m

ARM

To /F ro m

Input M essage

Bu ffer

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