STLC1510 datasheet(12/40 Pages) STMICROELECTRONICS

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STLC1510

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Figure 3. NIF Off-Chip Signals

The following tasks are performed by the ATM net-

work (in accordance with ITU-T Recommendation

I.432.1), and therefore do not have to be implement-

ed in the STLC1510 when using the CDIF:

HCS generation (Tx).

Payload scrambling (Tx).

Optionally, enables clear channel mode, in

which HCS generation and payload scrambling

are disabled (Tx).

HCS cell delineation (Rx).

Payload descrambling (Rx).

Idle cell filtering (Rx).

Header error detection to recover valid ATM

cells (header correction is not implemented)

(Rx).

Optionally, enables clear channel mode, in

which every 53 x 8 = 424 bits are collected by

the receiver and sent to the backplane (Rx).

5.1.4 UTOPIA Level 2 Interface and Controller

The Universal Test and Operations Physical Inter-

face for ATM (UTOPIA) provides a standard that links

ATM layer or various management entities with a va-

riety of physical (PHY) layers.

The UTOPIA IF has the following features:

provides clock decoupling mechanism.

throttles data flow from the ATM layer.

indicates to the ATM layer when the modem is

ready to receive data.

signals to the ATM layer the presence of valid

data for transmission.

Recognizes the address when the modem is

selected for communication.

Supports octet-level and/or cell-level

handshaking.

UTOPIA Level 2 supports a multi-PHY

operation for up to n PHY devices where,

n=< 8 at ATM layers intended for 155 Mbps;

U2PHY

URxData[7:1]

RxEnb

RxSOC

RxAddr[4:0]

CDIF

URxData[0]

RxClk

U2PHY

UTxData[7:1]

TxEnb

TxSOC

TxAddr[4:0]

TxClav

CDIF

UTxData[0]

TxClk

RxParity

TxParity

TxBP

RxClav

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