STLC1510 datasheet(22/40 Pages) STMICROELECTRONICS

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STLC1510

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5.11.1DFT Interfaces

The STLC1510 incorporates certain features (Design

for Testability, DFT) to improve the coverage of the fi-

nal production test. Certain pins are dedicated to this

features, and should not be used during normal oper-

ation. The Test Interface pins need to be connected

as follows:

5.11.2General Purpose I/O (GPIO) Interface

The STLC1510 has a 8-bit General Purpose I/O port

to allow low speed control and monitoring of external

signals via the LAMBA bus. The block diagram for

this interface is shown in Figure 8.

The GPIO has the following attributes:

There are 8 GPIO pins.

Each pin can be individually set to one of 4

modes:

• Input mode: Input signals will be sam-

pled with LAMBA bus clock and stored in

GPIO_in register.

• Output mode: The GPIO pin is driven

with the state in the GPIO_out register.

• Interrupt mode: The GPIO_int register

is set when there is a negative transition

detected on its corresponding GPIO pin.

The logic level of each interrupt pin will as

well be stored in the GPIO_in register. An

interrupt condition on any of the GPIO

pins will result in an interrupt to the D950.

• Dedicated mode. The GPIO pin is con-

figured to be its second function accord-

ing to the Table below If the pin does not

have a second function, it will be config-

ured as an input pin.

There is no external clock for the GPIO interface

and as such no timing defined.

Signal

BGA

Connected to

TCK

Pull-Up

TMS

Pull-Up

TDI

Pull-Up

TDO

open

TRSTN

See “RESET Structure” on

page 21.

Figure 8. GPIO Interface Block Diagram

Lam ba B u s I nterface (LBI )

La m b a

Bu s

GPIO _in

G PIO _out

GP IO _ int

GP IO [7:0]

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