STLC1510 datasheet(32/40 Pages) STMICROELECTRONICS

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Figure 18. GPIO Interface Timing

7.3 Power-up supply sequencing

There are two power supply voltages that must be

applied to this chip to ensure correct functionality,

(3.3V and 2.5V). The chip itself will function correctly

regardless of the sequence in which the supplies are

applied on power-up.

However if the 3.3V supply is off and there is external

5V activity at the IOs, the internal ESD protection cir-

cuitry will clamp the external signals at 2.8 Volts max-

imum (by sinking as much current as provided by the

interface).

8.0 EXTERNAL INTERFACE TIMING

8.1 NIF (Network Interface) Serial Interface

The NIF serial interface consists of separate clock

and data lines in the RX and TX directions. This inter-

face is illustrated briefly in Figure 19.

Figure 19. The NIF Serial Interface

In the Tx direction, the reception of a data byte from

the network starts with the most significant bit. Bits

are sampled by STLC1510 on the rising edge of Tx-

Clk. In the presence of clock gapping (which is gen-

erated by the STLC1510, as it supplies the clocks in

both directions), a previous bit persists until the next

rising edge of the clock. Figure 21. shows the rela-

tionship between TxClk and UTxData[0].

Table 18. GPIO Interface Timing

Pin Name

Parameter

Min.

Max.

Reference Pin

GPIO[1 :7]

tacc

10ns

w.r.t. rising GPIO[0]

GPIO[1 :7]

tse

5ns

w.r.t. rising GPIO[0]

GPIO[1 :7]

tho

2ns

w.r.t. rising GPIO[0]

G P IO [0]

ta c c

G P IO [1:7 ]

tse

th o

GP IO [1 :7 ]

TxCl k

Rx Clk

UTx Data[0]

UR xDa ta [0 ]

Ne two rk

STLC1510

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