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STLC1510 датащи(PDF) 35 Page - STMicroelectronics |
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STLC1510 датащи(HTML) 35 Page - STMicroelectronics |
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35 / 40 page ![]() 35/40 STLC1510 The TxBP pin is not part of the Utopia Level 2 speci- fication, but its functionality does not interfere with the operation of the Utopia Level 2 Interface. It can be left unconnected if necessary for a given application. This signal is described in more detail in the NIF chapter of this document. Features of MPHY Layer Cell-Level Handshake (Rx Direction): s A single MPHY port at a time is selected for a cell transmission. However, another MPHY port may be polled for its RxClav status while the selected MPHY port transfers data. The ATM layer polls the RxClav status of a MPHY port by placing its address on RxAddr. The MPHY port (STLC1510 device) drives RxClav during each cycle following one with its address on the RxAddr lines. s The ATM selects an MPHY port for transfer by placing the desired MPHY port address onto RxAddr, when RxEnb is deasserted (high) during the current clock cycle and asserted (low) during the following clock cycle. All MPHY devices examine the value on RxAddr for selection purposes when RxEnb is deasserted (high). The MPHY port is selected starting from the cycle after its address is on the RxAddr lines, and RxEnb is deasserted (low); and ending in the cycle a new MPHY port is addressed for selection, and RxEnb is deasserted (high). Figure 24. illustrates the timing diagram of the re- ceive interface when a cell is received from PHY N and the other PHYs are polled. Figure 24. UTOPIA Level 2 receive timing, polling phase and selection phase. Rx C lk Rx E nb URx Data Rx Clav Rx S O C N-1 P4 0 P41 P42 P4 3 P4 4 P4 5 P4 6 P4 7 P4 8 H 1H2H3 H4 1F 1F 1F 1F 1F 1F 1F N+1 N+ 3 N N+ 1 N+ 3 N-1 N-1 N+3 N+1 NN +3 N+1 Rx A d dr PH Y N PH Y N + 3 polling pollin g C ell tr an sm iss io n fr om : se le c tio n |
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