AD9174 datasheet(2/164 Pages) AD

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AD9174

Data Sheet

Rev. A | Page 2 of 164

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

Digital Specifications ................................................................... 5

Maximum DAC Sampling Rate Specifications......................... 5

Power Supply DC Specifications ................................................ 6

Serial Port and CMOS Pin Specifications ................................. 9

Digital Input Data Timing Specifications ............................... 10

JESD204B Interface Electrical and Speed Specifications ...... 11

Input Data Rates and Signal Bandwidth Specifications ........ 12

AC Specifications........................................................................ 13

Absolute Maximum Ratings.......................................................... 15

Reflow Profile.............................................................................. 15

Thermal Characteristics ............................................................ 15

ESD Caution................................................................................ 15

Pin Configuration and Function Descriptions........................... 16

Typical Performance Characteristics ........................................... 19

Terminology .................................................................................... 27

Theory of Operation ...................................................................... 28

Serial Port Operation ..................................................................... 30

Data Format ................................................................................ 30

Serial Port Pin Descriptions...................................................... 30

Serial Port Options..................................................................... 31

JESD204B Serial Data Interface.................................................... 32

JESD204B Overview .................................................................. 32

Physical Layer ............................................................................. 36

Data Link Layer .......................................................................... 38

Syncing LMFC Signals............................................................... 40

Transport Layer .......................................................................... 46

JESD204B Test Modes ............................................................... 47

JESD204B Error Monitoring..................................................... 49

Digital Datapath ............................................................................. 52

Total Datapath Interpolation .................................................... 52

Channel Digital Datapath ......................................................... 54

Main Digital Datapath............................................................... 57

NCO Only Mode........................................................................ 61

Modulator Switch....................................................................... 63

Interrupt Request Operation ........................................................ 67

Interrupt Service Routine.......................................................... 67

Analog Interface ............................................................................. 68

DAC Input Clock Configurations............................................ 68

Clock Output Driver.................................................................. 70

Analog Outputs .......................................................................... 70

Applications Information .............................................................. 72

Hardware Considerations ......................................................... 72

Start-Up Sequence.......................................................................... 75

Outline Dimensions..................................................................... 164

Ordering Guide ........................................................................ 164

REVISION HISTORY

5/2019—Rev. 0 to Rev. A

Change to Input Data Rate Per Input Channel Parameter,

Table 8 .............................................................................................. 12

Changes to Noise Spectral Density (NSD) Parameters,

Table 9 .............................................................................................. 13

Changes to Figure 16 Caption and Figure 17 Caption .............. 21

Change to Table 17 ......................................................................... 33

Changes to SYSREF± Sampling Section...................................... 41

Changes to Subclass 1 Section ...................................................... 42

Changes to Figure 73 and Table 37............................................... 55

Change to Complex Modulator Switch Configurations

Section.............................................................................................. 65

Changes to DAC On-Chip PL Section ........................................ 69

Change to M_DIVIDER_1 Bit Description, Table 52 ............... 75

Change to SPI_CHIPGRADE Register, Table 61....................... 82

Change to DATAPATH_NCO_SYNC_CFG Register,

Table 61 ............................................................................................ 85

Change to SPI_CHIPGRADE Register, Table 62....................... 94

Changes to DATAPATH_NCO_SYNC_CFG Register,

Table 62 .......................................................................................... 114

Changes to DACPLL_CTRL1 Register, Table 62 ..................... 155

11/2018—Revision 0: Initial Version

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