AD9174 datasheet(73/164 Pages) AD

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Data Sheet

AD9174

Rev. A | Page 73 of 164

If using the top layer of the PCB is problematic or the advantages of

stripline are desirable, follow these recommendations:

•

Minimize the number of vias.

•

If possible, use blind vias to eliminate via stub effects and

use microvias to minimize via inductance.

•

If using standard vias, use the maximum via length to

minimize the stub size. For example, on an 8-layer board,

use Layer 7 for the stripline pair (see Figure 94).

•

For each via pair, place a pair of ground vias adjacent to them

to minimize the impedance discontinuity (see Figure 94).

LAYER 1

LAYER 2

LAYER 3

LAYER 4

LAYER 5

LAYER 6

LAYER 7

LAYER 8

MINIMIZE STUB EFFECT

GND

DIFF–

DIFF+

ADD GROUND VIAS

STANDARD VIA

Figure 94. Minimizing Stub Effect and Adding Ground Vias for Differential

Stripline Traces

Return Loss

The JESD204B specification limits the amount of return loss

allowed in a converter device and a logic device but does not

specify return loss for the channel. However, make every effort

to maintain a continuous impedance on the transmission line

between the transmitting logic device and the AD9174.

Minimizing the use of vias, or eliminating them entirely,

reduces one of the primary sources for impedance mismatches

on a transmission line (see the Insertion Loss section). Maintain

a solid reference beneath (for microstrip) or above and below

(for stripline) the differential traces to ensure continuity in the

impedance of the transmission line. If the stripline technique is

used, follow the guidelines listed in the Insertion Loss section to

minimize impedance mismatches and stub effects.

Another primary source for impedance mismatch is at either

end of the transmission line, where care must be taken to match

the impedance of the termination to that of the transmission

line. The AD9174 handles this matching internally with a

calibrated termination scheme for the receiving end of the line.

See the Interface Power-Up and Input Termination section for

details on this circuit and the calibration routine.

Signal Skew

There are many sources for signal skew, but the two sources to

consider when laying out a PCB are interconnect skew within a

single JESD204B link and skew between multiple JESD204B

links. In each case, keeping the channel lengths matched to

within 10 mm (calculated by 12.5 mm × (12.5 Gbps/15.4 Gbps))

is adequate for operating the JESD204B link at speeds of up to

15.4 Gbps. This amount of channel length match is equivalent

to about 85% UI on the AD9174-FMC-EBZ evaluation board.

Managing the interconnect skew within a single link is

straightforward. Managing multiple links across multiple

devices is more complex. However, follow the 10 mm guideline

for length matching. The AD9174 can handle more skew than

the 85% UI due to the 6 PCLK buffer in the JESD204B receiver,

but matching the channel lengths as close as possible is still

recommended.

Topology

Structure the differential SERDINx± pairs to achieve 50 Ω to

ground for each half of the pair. Stripline vs. microstrip trade-

offs are described in the Insertion Loss section. In either case, it

is important to keep these transmission lines separated from

potential noise sources, such as high speed digital signals and

noisy supplies. If using stripline differential traces, route them

using a coplanar method, with both traces on the same layer.

Although this method does not offer more noise immunity than

the broadside routing method (traces routed on adjacent

layers), it is easier to route and manufacture so that the

impedance continuity is maintained. Broadside vs. coplanar

differential transmitter (Tx) lines are shown in Figure 95.

Tx DIFF A

DIFF A

DIFF B

ACTIVE

Tx DIFF B

Tx ACTIVE

BROADSIDE DIFFERENTIAL Tx LINES

COPLANAR DIFFERENTIAL Tx LINES

Figure 95. Broadside vs. Coplanar Differential Stripline Routing Techniques

When considering the trace width vs. copper weight and

thickness, the speed of the interface must be considered. At

multigigabit speeds, the skin effect of the conducting material

confines the current flow to the surface. Maximize the surface

area of the conductor by making the trace width wider to

reduce the losses. Additionally, loosely couple differential traces

to accommodate the wider trace widths. This coupling helps

reduce the crosstalk and minimize the impedance mismatch

when the traces must separate to accommodate components,

vias, connectors, or other routing obstacles. Tightly coupled vs.

loosely coupled differential traces are shown in Figure 96.

DIFF A

DIFF B

TIGHTLY COUPLED

DIFFERENTIAL Tx LINES

LOOSELY COUPLED

DIFFERENTIAL Tx LINES

Figure 96. Tightly Coupled vs. Loosely Coupled Differential Traces

AC Coupling Capacitors

The AD9174 requires that the JESD204B input signals be

ac-coupled to the source. These capacitors must be 100 nF and

placed as close as possible to the transmitting logic device. To

minimize the impedance mismatch at the pads, select the

package size of the capacitor so that the pad size on the PCB

matches the trace width as closely as possible.

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