AD9174 datasheet(76/164 Pages) AD

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AD9174

Data Sheet

Rev. A | Page 76 of 164

R/W

Bits

Value

Description

0x094

[7:2]

0x00

Keep default value for these bits.

PLL_VCO_DIV3_EN

Enable PLL output clock to be divided by 3. If this bit is set to 1, DAC clock = PLL VCO

frequency/3.

PLL_VCO_DIV2_EN

Enable PLL output clock to be divided by 2. Either this bit or Bit 1 in this register can be set

to 1, but both bits cannot be set at the same time (there is no divide by 6 option).

0b0: DAC clock = PLL VCO frequency.

0b1: DAC clock = PLL VCO frequency/2.

0x792

[7:0]

0x02

Reset VCO.

0x792

[7:0]

0x00

Pause

Wait 100 ms for PLL to lock.

0x7B5

0b1

Ensure PLL is locked by reading back a value of 1 for bit 0 of this register.

Table 53. Delay Lock Loop (DLL) Configuration

R/W

Bits

Value

Description

0x0C0

[7:0]

0x00

Power-up delay line.

0x0DB

[7:0]

0x00

0x0DB

[7:0]

0x01

Update DLL settings to circuitry.

0x0DB

[7:0]

0x00

0x0C1

[7:0]

0x68 or 0x48

Set DLL search mode. If fDAC is < 4.5 GHz, set this register to 0x48. Otherwise, set this register to 0x68.

0x0C1

[7:0]

0x69 or 0x49

Set DLL search mode. If fDAC is < 4.5 GHz, set this register to 0x49. Otherwise, set this register to 0x69.

0x0C7

[7:0]

0x01

Enable DLL read status.

0x0C3

0b1

Ensure DLL is locked by reading back a value of 1 for Bit 0 of this register.

Table 54. Calibration

R/W

Bits

Value

Description

0x050

[7:0]

0x2A

Optimized calibration setting register write.

0x061

[7:0]

0x68

Required calibration control register write.

0x051

[7:0]

0x82

Optimized calibration setting register write.

0x051

[7:0]

0x83

Required calibration control register write.

0x081

[7:0]

0x03

Required calibration control register write.

Table 55. JESD204B Mode Setup

R/W

Bits

Value

Description

0x100

[7:0]

0x00

Power up digital datapath clocks when internal clocks are stable.

0x110

[5:0]

JESD_MODE

Bit 5 of the JESD_MODE bit field determines whether the device is operating in single link

or dual link modes. 0 = single-link mode; 1 = dual-link mode. Bits[4:0] determine the

SERDES JESD204B mode of operation chosen from the appropriate single-link or dual-link

modes in Table 15 or Table 16.

0x111

[7:4]

DP_INTERP_MODE

Main datapath interpolation mode. The valid interpolation options for this control is based on

the JESD_MODE selected in Register 0x110. Bit 7 of Register 0x110 equals 1 if the JESD_MODE,

DP_INTERP_MODE, and CH_INTERP_MODE settings are not a valid combination.

[3:0]

CH_INTERP_MODE

Channel datapath interpolation mode. The valid interpolation options for this control is based

on the JESD_MODE selected in Register 0x110. Bit 7 of Register 0x110 equals 1 if the

JESD_MODE, DP_INTERP_MODE, and CH_INTERP_MODE settings are not a valid combination.

0x084

SYSREF_INPUTMODE

SYSREF± signal input mode selection.

0b0 = ac-coupled.

0b1 = dc-coupled.

SYSREF_PD

If using Subclass 0, this bit can be set to 1 to power down the SYSREF± receiver. If using

Subclass 1, keep at the default of 0.

0x312

[7:4]

Set SYNCOUTx± error duration, depending on the selected mode.

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