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Data Sheet

AD9174

Rev. A | Page 49 of 164

12. Choose another sample for the same or another M to

continue with the test, until all samples for both converters

from one frame are verified.

Repeated CGS and ILAS Test

As per Section 5.3.3.8.2 of the JESD204B specification, the

AD9174 can check that a constant stream of /K28.5/ characters

is being received, or that CGS followed by a constant stream of

ILAS is being received.

To run a repeated CGS test, send a constant stream of /K28.5/

characters to the AD9174 SERDES inputs. Next, set up the

device and enable the links. Ensure that the /K28.5/ characters are

being received by verifying that SYNCOUT± is deasserted and

that CGS has passed for all enabled link lanes by reading

To run the CGS followed by a repeated ILAS sequence test,

follow the procedure to set up the links, but before performing

the last write (enabling the links), enable the ILAS test mode by

writing a 1 to Register 0x477, Bit 7. Then, enable the links. When

the device recognizes four CGS characters on each lane, it

deasserts the SYNCOUTx±. At this point, the transmitter starts

sending a repeated ILAS sequence.

Read Register 0x473 to verify that the initial lane synchronization

has passed for all enabled link lanes.

JESD204B ERROR MONITORING

Disparity, Not in Table, and Unexpected Control (K)

Character Errors

As per Section 7.6 of the JESD204B specification, the AD9174 can

detect disparity errors, not in table (NIT) errors, and unexpected

control character errors, and can optionally issue a sync request

and reinitialize the link when errors occur.

Several other interpretations of the JESD204B specification are

noted in this section. When three NIT errors are injected to one

lane and QUAL_RDERR (Register 0x476, Bit 4) = 1, the readback

values of the bad disparity error (BDE) count register is 1.

Reporting of disparity errors that occur at the same character

position of an NIT error is disabled. No such disabling is per-

formed for the disparity errors in the characters after an NIT

error. Therefore, it is expected behavior that an NIT error may

result in a BDE error.

Checking Error Counts

The error count can be checked for disparity errors, NIT errors,

and unexpected control character errors. The error counts are

on a per lane and per error type basis. Each error type and lane

has a register dedicated to it. To check the error count, the

following steps must be performed:

1. Choose and enable which errors to monitor by selecting

them in Register 0x480, Bits[5:3] to Register 0x487, Bits[5:3].

Unexpected K (UEK) character, BDE, and NIT error

monitoring can be selected for each lane by writing a 1 to

the appropriate bit, as described in Table 62. These bits are

enabled by default.

2. The corresponding error counter reset bits are in

Write a 1 to the corresponding bit to reset that error

counter.

3. Registers 0x488, Bits[2:0] to Register 0x48F, Bits[2:0] have

the terminal count hold indicator for each error counter. If

this flag is enabled, when the terminal error count of 0xFF

is reached, the counter ceases counting and holds that

value until reset. Otherwise, it wraps to 0x00 and continues

counting. Select the desired behavior and program the

corresponding register bits per lane.

Check for Error Count Over Threshold

To check for the error count over threshold, follow these steps:

1. Define the error counter threshold. The error counter

threshold can be set to a user defined value in Register 0x47C,

or left to the default value of 0xFF. When the error threshold is

reached, an IRQ is generated, SYNCOUTx± is asserted, or

both, depending on the mask register settings. This one error

threshold is used for all three types of errors (UEK, NIT,

and BDE).

2. Set the SYNC_ASSERT_MASK bits. The SYNCOUTx±

assertion behavior is set in Register 0x47D, Bits[2:0]. By

default, when any error counter of any lane is equal to

the threshold, it asserts SYNCOUTx± (Register 0x47D,

Bits[2:0] = 0b111). When setting the SYNC_ASSERT_MASK

bits, LINK_PAGE (Register 0x300, Bit 2) must be set to 1.

3. Read the error count reached indicator. Each error counter

has a terminal count reached indicator, per lane. This indica-

tor is set to 1 when the terminal count of an error counter

for a particular lane is reached. These status bits are located

in Register 0x490, Bits[2:0] to Register 0x497, Bits[2:0]. Bit 3

can be read back to indicate whether a particular lane is

active.

Error Counter and IRQ Control

For error counter and IRQ control, follow these steps:

1. Enable the interrupts. Enable the JESD204B interrupts. The

interrupts for the UEK, NIT, and BDE error counters are in

monitor when bringing up the link, such as lane deskewing,

initial lane sync, good check sum, frame sync, code group sync

(Register 0x4B8, Bits[4:0], and configuration mismatch

(Register 0x4B9, Bit 0). These bits are off by default but can

be enabled by writing 0b1 to the corresponding bit.

2. Read the JESD204B interrupt status. The interrupt status

bits are in Register 0x4BA, Bits[7:0] and Register 0x4BB,

Bit 0, with the status bit position corresponding to the

enable bit position.

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