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AD9174 датащи(PDF) 97 Page - Analog Devices

номер детали AD9174
подробное описание детали  Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
PDF  164 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9174 датащи(HTML) 97 Page - Analog Devices

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Data Sheet
AD9174
Rev. A | Page 97 of 164
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0
IRQ_PLL_LOCK
DAC PLL locked. If EN_PLL_LOCK is low, IRQ_
PLL_LOCK shows the current status. If EN_
PLL_LOCK is high, IRQ_PLL_LOCK latches
and pulls the
A
IRQxE
A
pin low (x = MUX_PLL_
LOCK setting). Writing a 1 to IRQ_PLL_LOCK
when latched clears the bit.
0x0
R/W
0x028
IRQ_OUTPUT_MUX
[7:5]
RESERVED
Reserved.
0x0
R
4
MUX_SYSREF_
JITTER
If EN_SYSREF_JITTER is set, this control
chooses the
A
IRQxE
A
output pin on which the
event is triggered.
0x0
R/W
0
Route IRQ trigger signal to the
A
IRQ0E
A
pin.
1
Route IRQ trigger signal to the
A
IRQ1E
A
pin.
3
MUX_DATA_READY
If EN_DATA_READY is set, this control
chooses the
A
IRQxE
A
output pin on which the
event is triggered.
0x0
R/W
0
Route IRQ trigger signal to the
A
IRQ0E
A
pin.
1
Route IRQ trigger signal to the
A
IRQ1E
A
pin.
2
MUX_LANE_FIFO
If EN_LANE_FIFO is set, this control chooses
the
A
IRQxE
A
output pin on which the event is
triggered.
0x0
R/W
0
Route IRQ trigger signal to the
A
IRQ0E
A
pin.
1
Route IRQ trigger signal to the
A
IRQ1E
A
pin.
1
MUX_PRBSQ
If EN_PRBSQ is set, this control chooses the
A
IRQxE
A
output pin on which the event is
triggered.
0x0
R/W
0
Route IRQ trigger signal to the
A
IRQ0E
A
pin.
1
Route IRQ trigger signal to the
A
IRQ1E
A
pin.
0
MUX_PRBSI
If EN_PRBSI is set, this control chooses the
A
IRQxE
A
output pin on which the event is
triggered.
0x0
R/W
0
Route IRQ trigger signal to the
A
IRQ0E
A
pin.
1
Route IRQ trigger signal to the
A
IRQ1E
A
pin.
0x029
IRQ_OUTPUT_MUX0
[7:4]
RESERVED
Reserved.
0x0
R
3
MUX_DAC0_CAL_
DONE
If EN_DAC0_CAL_DONE is set, this control
chooses the
A
IRQxE
A
output pin on which the
event is triggered.
0x0
R/W
0
Route IRQ trigger signal to the
A
IRQ0E
A
pin.
1
Route IRQ trigger signal to the
A
IRQ1E
A
pin.
[2:1]
RESERVED
Reserved.
0x0
R/W
0
MUX_PAERR0
If EN_PAERR0 is set, this control chooses
the
A
IRQxE
A
output pin on which the event is
triggered.
0x0
R/W
0
Route IRQ trigger signal to the
A
IRQ0E
A
pin.
1
Route IRQ trigger signal to the
A
IRQ1E
A
pin.
0x02A
IRQ_OUTPUT_MUX1
[7:4]
RESERVED
Reserved.
0x0
R
3
MUX_DAC1_CAL_
DONE
If EN_DAC1_CAL_DONE is set, this control
chooses the
A
IRQxE
A
output pin on which the
event is triggered.
0x0
R/W
0
Route IRQ trigger signal to the
A
IRQ0E
A
pin.
1
Route IRQ trigger signal to the
A
IRQ1E
A
pin.
[2:1]
RESERVED
Reserved.
0x0
R/W



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