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AD9174

Data Sheet

Rev. A | Page 32 of 164

JESD204B SERIAL DATA INTERFACE

JESD204B OVERVIEW

The AD9174 has eight JESD204B SERDES data ports that receive

the input sample data to the device. The eight JESD204B ports

can be combined to form either one (single-link) or two (dual-

link) identical JESD204B links. Each link can provide data to its

own datapath with its own set of channelizers.

Both single- and dual-link JESD204B modes align their individual

(local) clocks to the same system reference (SYSREF±) and device

clock (CLKIN±) signals. However, the SYNCOUT0± and

SYNCOUT1± signals are specific to their respective JESD204B

link, and in dual-link mode the two links can operate

independently from one another.

The JESD204B serial interface hardware is grouped into three

layers: the physical layer, the data link layer, and the transport layer.

Figure 52 shows the three communication layers implemented in

the AD9174 serial data interface to recover the clock and

deserialize, descramble, and deframe the data before it is sent to

each of the digital signal processing channelizers of the device.

The communication layers are described as follows:

•

The physical layer establishes a reliable channel between

the transmitter and the receiver.

•

The data link layer is responsible for unpacking the data

into octets and descrambling the data.

•

The transport layer receives the descrambled JESD204B

frames and converts them to DAC samples.

A detailed description of each layer is provided in the subsequent

sections, including information for configuring each aspect of

the interface.

A number of JESD204B parameters (L, F, K, M, N, NP, S, HD)

defines how the data is packed and tells the device how to turn

the serial data into samples. These parameters are described in

detail in the Transport Layer section. The AD9174 also has a

descrambling option (see the Descrambler section for more

information). To increase the maximum data rate achievable by

the SERDES interface, the AD9174 has the ability to use a 12-bit

packing mode (NP = 12, N = 11 or 12) for applications that do

not require 16-bit data.

The AD9174 has multiple JESD204B modes, which include

single- and dual-link modes, and allow configuration of the

device depending on the number channels, number of DAC

cores, and link speed requirements. These modes and their

respective JESD204B link parameters are described in Table 15

and Table 16. Various combinations of channel interpolation

and main datapath interpolation are available, depending on the

mode. Table 13 lists all the possible link and interpolation

combinations available as well as the maximum supported data

rate for each mode.

The AD9174 has two DAC cores, each with its own analog output.

Each DAC core is supplied with data from as many as three

complex channelizers. The effective number of converters, as

seen by the JESD204B link, is the number of noncomplex

channels in the given mode of operation, as represented by the

M parameter of the JESD204B standard. Therefore, a single

noncomplex channel is represented by M = 1, a complex channel is

represented by M = 2, a group of two complex channels is

represented by M = 4, and so on. When the total datapath

interpolation is set to 1×, the complex channels are bypassed

and the data input is assumed to be noncomplex (real). In this

case only, M = 2 represents the actual number of DAC cores,

and the complex data is not required.

For a particular JESD204B mode of operation, the following

relationships exist:

Total Interpolation = Channel Interpolation ×

Main Interpolation

Data Rate = DAC Rate/Total Interpolation

Lane Rate = (M/L) × NP × (10/8) × Data Rate

where:

Lane Rate must be between 3 Gbps and 15.4 Gbps.

M, L, and NP are JESD204B link parameters for the chosen

JESD204B operating mode.

Achieving and maintaining synchronous operation between the

JESD204B transmitter and the JESD204B receiver is critical for

maintaining a reliable link. After the link is established, the stability

and phase relationship between the various system clocks becomes

important. If a particular clock slips relative to a common

reference, the link may be lost and may need to be reestablished.

Similarly, if a particular lane becomes asynchronous relative to

other lanes within the link, this link may be lost as well. To simplify

the process of establishing or reestablishing a link, the AD9174

designates an independent master synchronization signal for each

JESD204B link. The SYNCOUT0± and SYNCOUT1± pins are

used as the master flag signal for all the lanes in the particular link.

If the data arriving on the various lanes appears to be out of

synchronization, SYNCOUTx± is deasserted and the transmitter

is expected to stop sending data and instead begin sending

synchronization characters to all the lanes in that link until

resynchronization is achieved.

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