AD9174 datasheet(72/164 Pages) AD

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AD9174

Data Sheet

Rev. A | Page 72 of 164

APPLICATIONS INFORMATION

HARDWARE CONSIDERATIONS

Power Supply Recommendations

All the AD9174 supply domains must remain as noise free as

possible for the best operation. Power supply noise has a frequency

component that affects performance, and is specified in V rms.

An LC filter on the output of the power supply is recommended

to attenuate the noise, and must be placed as close to the AD9174

as possible. The AVDD1.0 supply, which supplies the clock receiver

and DAC analog core circuitry, and the AVDD1.8 supply, which

powers the DAC output and DAC PLL blocks, are the most noise

sensitive supplies on the device. It is highly recommended that

AVDD1.0 and AVDD1.8 be supplied separately with ultralow

noise regulators, such as the ADP1763 and ADM7154 or better

to achieve the best phase noise performance possible. Noisier

regulators impose phase noise onto the DAC output.

The DVDD1.0 supply provides power to the digital datapath

blocks and the SVDD1.0 supply powers the SERDES circuitry

on the chip. The DVDD1.8 supply powers circuitry blocks

related to the SPI, SYNCOUTx± transmitter, SYSREF receiver,

IRQx, RESET, and TXENx circuitry.

Take note of the maximum power consumption numbers

shown in Table 4 to ensure the power supply design can tolerate

temperature and IC process variation extremes. The amount of

current drawn is dependent on the chosen use cases, and

specifications are provided for several use cases to illustrate

examples and contributions from individual blocks, and to

assist in calculating the maximum required current per supply.

Another consideration for the power supply design is peak

current handling capability. The AD9174 draws more current

in the main digital supply when synthesizing a signal with

significant amplitude variations, such as a modulated signal,

as compared to when in idle mode or synthesizing a dc signal.

Therefore, the power supply must be able to supply current

quickly to accommodate burst signals such as GSM, TDMA,

or other signals that have an on or off time domain response.

Because the amount of current variation depends on the signals

used, it is best to perform lab testing first to establish ranges. A

typical difference can be several hundred milliamperes.

Power and Ground Planes

Solid ground planes are recommended to avoid ground loops

and to provide a solid, uninterrupted ground reference for the

high speed transmission lines that require controlled impedances.

It is recommended that power planes be stacked between ground

layers for high frequency filtering. Doing so adds extra filtering

and isolation between power supply domains in addition to the

decoupling capacitors.

Do not use segmented power planes as a reference for controlled

impedances unless the entire length of the controlled impedance

trace traverses across only a single segmented plane. These and

additional guidelines for the topology of high speed transmission

lines are described in the JESD204B Serial Interface Inputs

(SERDIN0± to SERDIN7±) section.

For some applications, where highest performance and higher

output frequencies are required, the choice of PCB materials

significantly impacts results. For example, materials such as

polyimide or materials from the Rogers Corporation can be

used, for example, to improve tolerance to high temperatures

and improve performance. Rogers 4350 material is used for the

top three layers in some of the evaluation board designs:

between the top signal layer and the ground layer below it.

JESD204B Serial Interface Inputs (SERDIN0± to SERDIN7±)

When considering the layout of the JESD204B serial interface

transmission lines, there are many factors to consider to

maintain optimal link performance. Among these factors are

insertion loss, return loss, signal skew, and the topology of the

differential traces.

Insertion Loss

The JESD204B specification limits the amount of insertion loss

allowed in the transmission channel (see Figure 56). The AD9174

equalization circuitry allows significantly more loss in the channel

than is required by the JESD204B specification. It is still important

that the designer of the PCB minimize the amount of insertion

loss by adhering to the following guidelines:

•

Keep the differential traces short by placing the AD9174 as

close to the transmitting logic device as possible and routing

the trace as directly as possible between the devices.

•

Route the differential pairs on a single plane using a solid

ground plane as a reference. It is recommended to route

the SERDES lanes on the same layer as the AD9174 to

avoid vias being used in the SERDES lanes.

•

Use a PCB material with a low dielectric constant (<4) to

minimize loss, if possible.

When choosing between the stripline and microstrip techniques,

keep in mind the following considerations: stripline has less loss

(see Figure 57 and Figure 58) and emits less EMI, but requires

the use of vias that can add complexity to the task of controlling

the impedance. The microstrip technique is easier to implement

(if the component placement and density allow routing on the

top layer) and eases the task of controlling the impedance.

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