TPS65982ABZBHR datasheet(97/121 Pages) TI1

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TPS65982

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SLVSD02D – MARCH 2015 – REVISED JUNE 2019

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Layout Guidelines (continued)

Table 19. Routing Trace Widths (continued)

ROUTE

WIDTH (mil)

LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VIN_3V3,

VOUT_3V3, VDDIO, HV_GATE1, HV_GATE2

Component GND

12.1.9 Void Via Placement

The void under the TPS65982 is used to via out I/O and for thermal relief vias. A minimum of 6 vias must be

used for thermal dissipation to the GND planes. The thermal relief vias must be placed on the right side of the

device by the power path. Figure 101 shows the recommended placement of the vias. Note the areas under the

void where vias are not placed. This is done to allow the external FET gate drive and sense pins to route under

the TPS65982 through an inner layer. Figure 102 shows the top layer GND pour to connect the vias and GND

balls together.

12.1.10 Top Layer Routing

Once the components are routed, the rest of the area can be used to route all of the additional I/O. After all nets

have been routed place a polygonal pour under to connect the TPS65982 GND pins to the GND vias. Refer to

Figure 103 for the final top routing and GND pour.

12.1.11 Inner Signal Layer Routing

The inner signal layer is used to route the I/O from the internal balls of the TPS65982 and the external FET

control and sensing. Figure 104 shows how to route the internal layer.

12.1.12 Bottom Layer Routing

The bottom layer has most of the components placed and routed already. Place a polygon pour to connect all of

the GND nets and vias on the bottom layer, refer to Figure 105.

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