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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TPS65982ABZBHR датащи(PDF) 59 Page - Texas Instruments |
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TPS65982ABZBHR датащи(HTML) 59 Page - Texas Instruments |
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59 / 121 page  SWD_CLK SWD_DATA UART_TX UART_RX LSX_P2R LSX_R2P R_OSC GPIO0-8 BUSPOWERZ I2C_SDA1 I2C_SCL1 I2C_IRQ1Z I2C_SDA2 I2C_SCL2 I2C_IRQ2Z I2C_ADDR SPI_CLK SPI_MOSI SPI_MISO SPI_SSZ Digital Core SWD UART0 UART1 ADC Temp Sense USB EP Phy Signals into ADC USB EP Thermal Shutdown CBL_DET Bias CTL and USB-PD SPI Port 2 Phy USB PD Port 1 OSC Debug Port DEBUG_CTL1 DEBUG_CTL2 I C to 2 System Control I C to 2 Auxiliary Control SPI to Flash RESETZ MRESET HRESET ADC Read I C 2 I C 2 I C 2 59 TPS65982 www.ti.com SLVSD02D – MARCH 2015 – REVISED JUNE 2019 Product Folder Links: TPS65982 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated The enabling of the switch is controlled by the core digital circuitry and the conditions are programmable. A supervisor circuit monitors the voltage at VOUT_3V3 for an undervoltage condition and sets the external indicator RESETZ. The RESETZ pin is active low (low when an undervoltage condition occurs). The RESETZ output is also asserted when the MRESET input is asserted. The MRESET input is active-high by default, but is configurable to be active low. Figure 4 shows the RESETZ timing with MRESET set to active high. When VOUT_3V3 is disabled, a resistance of RPDOUT_3V3 pulls down on the pin. 9.3.6 Digital Core Figure 50 shows a simplified block diagram of the digital core. This diagram shows the interface between the digital and analog portions of the TPS65982. Figure 50. Digital Core Block Diagram 9.3.7 USB-PD BMC Modem Interface The USB-PD BMC modem interface is a fully USB-PD compliant Type-C interface. The modem contains the BMC encoder/decoder, the TX/Rx FIFOs, the packet engine for construction/deconstruction of the USB-PD packet. This module contains programmable SOP values and processes all SOP headers. |
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