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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TPS65982ABZBHR датащи(PDF) 23 Page - Texas Instruments |
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TPS65982ABZBHR датащи(HTML) 23 Page - Texas Instruments |
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23 / 121 page  23 TPS65982 www.ti.com SLVSD02D – MARCH 2015 – REVISED JUNE 2019 Product Folder Links: TPS65982 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated Input/Output (I/O) Characteristics (continued) Recommended operating conditions; TA = –10 to 85°C unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (1) DEBUG_CTL1/2 do not have an internal pulldown resistance path. SWDIO SWDIO_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V SWDIO_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V SWDIO_HYS Input hysteresis voltage LDO_3V3 = 3.3 V 0.2 V SWDIO_ILKG Leakage current Output is Hi-Z, VIN = 0 V to LDO_3V3 –1 1 μA SWDIO_VOH Output high voltage IO = –8 mA, LDO_3V3 = 3.3 V 2.9 V IO = –15 mA, LDO_3V3 = 3.3 V 2.5 SWDIO_VOL Output low voltage IO = 10 mA 0.4 V IO = 20 mA 0.8 SWDIO_RPU Pullup resistance 2.8 4 5.2 kΩ SWDIO_TOS SWDIO output skew to falling edge SWDCLK –5 5 ns SWDIO_TIS Input setup time required between SWDIO and rising edge of SWCLK 6 ns SWDIO_TIH Input hold time required between SWDIO and rising edge of SWCLK 1 ns SWDCLK SWDCL_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V SWDCL_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V SWDCL_THI SWDIOCLK HIGH period 0.05 500 μs SWDCL_TLO SWDIOCLK LOW period 0.05 500 μs SWDCL_HYS Input hysteresis voltage LDO_3V3 = 3.3 V 0.2 V SWDCL_RPU Pullup resistance 2.8 4 5.2 kΩ GPIO (GPIO0-8, DEBUG1-4, DEBUG_CTL1/2, MRESET, RESETZ, BUSPOWERZ) GPIO_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V VDDDIO = 1.8 V 1.25 GPIO_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V VDDIO = 1.8 V 0.63 GPIO_HYS Input hysteresis voltage LDO_3V3 = 3.3 V 0.2 V VDDIO = 1.8 V 0.09 GPIO_ILKG Leakage current Pin is Hi-Z; VIN = 0 V to VDD (VDDIO or LDO_3V3) –1 1 μA GPIO_RPU Pullup resistance (GPIO0-8, DEBUG1-4, MRESET, RESETZ, BUSPOWERZ) Pullup enabled 50 100 150 kΩ Pullup resistance (DEBUG_CTL1/2) Pullup enabled 2.5 5 7.5 GPIO_RPD Pulldown resistance (GPIO0-8, DEBUG1-4, MRESET, RESETZ, BUSPOWERZ)(1) Pulldown enabled 50 100 150 kΩ GPIO_DG Digital input path deglitch 20 ns GPIO_VOH Output high voltage IO = –2 mA, LDO_3V3 = 3.3 V 2.9 V IO = –2 mA, VDDIO = 1.8 V 1.35 GPIO_VOL Output low voltage IO = 2 mA, LDO_3V3 = 3.3 V 0.4 V IO = 2 mA, VDDIO = 1.8 V 0.45 HRESET HRESET_VIH High-level input voltage 1.25 V HRESET_VIL Low-level input voltage 0.63 V HRESET_HYS Input hysteresis Voltage 0.09 V HRESET_ILKG I/O leakage current VIN = 0 V to LDO_1V8D –1 1 μA HRESET_THIGH HRESET minimum high time to assert a reset condition 2.0 ms HRESET_TLOW HRESET minimum low time to deassert a reset condition 2.0 UART_RX/TX, LSX_P2R/R2P |
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