TPS65982ABZBHR datasheet(96/121 Pages) TI1

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TPS65982

SLVSD02D – MARCH 2015 – REVISED JUNE 2019

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Layout Guidelines (continued)

12.1.4 Oval Pad Footprint Layout and Placement

The oval pad footprint layout is generally more difficult to route than the standard footprint because of the top

layer fan-out and void via placement needed; however, when the footprint with oval pads is used, Via on Pads,

laser-drilled vias, and HDI board processes are not required. Therefore, a footprint with oval pads is ideal for

cost-optimized applications and will be used for the following the layout example. This layout example follows the

charger application example (see Typical Applications) and includes all necessary passive components needed

for this application. This design uses both the internal and optional external FET paths for sourcing and sinking

power respectively. Follow the differential impedances for High Speed signals defined by their specifications

(DisplayPort - AUXN/P and USB2.0). All I/O will be fanned out to provide an example for routing out all pins, not

all designs will use all of the I/O on the TPS65982.

12.1.5 Component Placement

Placement of components on the top and bottom layers is used for this example to minimize solution size. The

TPS65982 is placed on the top layer of the board and the majority of its components are placed on the bottom

layer. When placing the components on the bottom layer, it is recommended that they are placed directly under

the TPS65982 in a manner where the pads of the components are not directly under the void on the top layer.

Figure 92 and Figure 93 show the placement in 2-D. Figure 94 and Figure 95 show the placement in 3-D.

12.1.6 Designs Rules and Guidance

When starting to route nets it is best to start with 4 mil clearance spacing. The designer may have to adjust the

4mil clearance to 3.5 mil when fanning out the top layer routes. With the routing of the top layer having a tight

clearance, it is recommended to have the layout grid snapped to 1 mil. For certain routes on the layout done in

this guide, the grid snap was set to 0.1 mil. For component spacing this design used 20 mil clearance between

components. The silk screen around certain passive components may be deleted to allow for closer placement of

components.

12.1.7 Routing PP_HV, PP_EXT, PP_5V0, and VBUS

On the top layer, create pours for PP_HV, PP_5V0 and VBUS to extend area to place 8 mil hole and 16 mil

diameter vias to connect to the bottom layer. A minimum of 4 vias is needed to connect between the top and

bottom layer. For the bottom layer, place pours that will connect the PP_HV, PP_5V0, and VBUS capacitors to

their respective vias. The external FETS must also be connected through pours and place vias for the external

FET gates. For 5 A systems, special consideration must be taken for ensuring enough copper is used to handle

the higher current. For 0.5 oz copper top or bottom pours with 0.5-oz plating will require approximately a 120-mil

pour width for 5-A support. When routing the 5 A through a 0.5 oz internal layer, more than 200 mil will be

required to carry the current. Figure 96 and Figure 97 show the pours used in this example.

12.1.8 Routing Top and Bottom Passive Components

The next step is to route the connections to the passive components on the top and bottom layers. For the top

layer only CC1 and CC2 capacitors will be placed on top. Routing the CC1 and CC2 lines with a 8 mil trace will

facilitate the needed current for supporting powered Type C cables through VCONN. For more information on

VCONN please refer to the Type C specification. Figure 98 shows how to route to the CC1 and CC2 to their

respective capacitors. For capacitor GND pin use a 10 mil trace if possible. This particular system support Dead

Battery, which has RPD_G1/2 connected to CC1/2.

The top layer pads will have to be connected the bottom placed component through Vias (8 mil hole and 16 mil

diameter recommended). For the VIN_3V3, VDDIO, LDO_3V3, LDO_1V8A, LDO1V8D, LDO_BMC, and

VOUT_3V3 use 6mil traces to route. For PP_CABLE route using an 8 mil trace and for all other routes 4 mil

traces may be used. To allow for additional space for routing, stagger the component vias to leave room for

routing other signal nets. Figure 99 and Figure 100 show the top and bottom routing. Table 19 provides a

summary of the trace widths.

Table 19. Routing Trace Widths

ROUTE

WIDTH (mil)

CC1, CC2, PP_CABLE

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