TPS65982ABZBHR datasheet(77/121 Pages) TI1

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Start Condition

Stop Condition

SDA

SCL

TPS65982

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SLVSD02D – MARCH 2015 – REVISED JUNE 2019

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Programming (continued)

9.5.2 I2C Slave Interface

The TPS65982 has three I2C interface ports. I2C Port 1 is comprised of the I2C_SDA1, I2C_SCL1, and

I2C_IRQ1Z pins. I2C Port 2 is comprised of the I2C_SDA2, I2C_SCL2, and I2C_IRQ2Z pins. These interfaces

provide general status information about the TPS65982, as well as the ability to control the TPS65982 behavior,

as well as providing information about connections detected at the USB-C receptacle and supporting

communications to and from a connected device, cable supporting BMC USB-PD, or both. The third port is

comprised of the DEBUG_CTL1 and DEBUG_CTL2 pins. This third port is a firmware emulated I2C master. The

pins are generic GPIO and do not contain any dedicated hardware for I2C such as detecting starts, stops, acks,

or other protocol normally associated with I2C. This third port is always a master and has no interrupt. This port is

intended to master another device that has simple control based on mode and multiplexer orientation.

DEBUG_CTL1 is the serial clock and DEBUG_CTL2 is serial data.

The first two ports can be a master or a slave, but the default behavior is to be a slave. Port 1 and Port 2 are

interchangeable. Each port operates the same way and has the same access in and out of the core. An interrupt

mask is set for each that determines what events are interrupted on that given port.

9.5.2.1 I2C Interface Description

The TPS65982 support Standard and Fast mode I2C interface. The bidirectional I2C bus consists of the serial

clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pullup resistor. Data

transfer may be initiated only when the bus is not busy.

A master sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is high

initiates I2C communication. After the Start condition, the device address byte is sent, most significant bit (MSB)

first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA

input/output during the high of the ACK-related clock pulse. On the I2C bus, only one data bit is transferred

during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period

as changes in the data line at this time are interpreted as control commands (Start or Stop). The master sends a

Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high.

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a

slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must

generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to

ensure proper operation

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after

the last byte has been clocked out of the slave. The master receiver holding the SDA line high does this. In this

event, the transmitter must release the data line to enable the master to generate a Stop condition.

Figure 70 shows the start and stop conditions of the transfer. Figure 71 shows the SDA and SCL signals for

transferring a bit. Figure 72 shows a data transfer sequence with the ACK or NACK at the last clock pulse.

Figure 70. I2C Definition of Start and Stop Conditions

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