TPS65982ABZBHR datasheet(76/121 Pages) TI1

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Send “Request

Data” Packet

Boot Fail

Receive “Send

Data” Packet &

Save Data

Receive “Send

CRC” packet

Saved Data

valid

Run App Code

Block map

complete

Send “Send Data”

packet

Send “Send CRC”

Packet

Receive “Request

Data” Packet

Yes

Primary

Secondary

SPI_MISO

Low

App Code Loaded

TPS65982

SLVSD02D – MARCH 2015 – REVISED JUNE 2019

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Product Folder Links: TPS65982

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Device Functional Modes (continued)

Figure 69. UART Download Process

9.5 Programming

9.5.1 SPI Master Interface

The TPS65982 loads flash memory during the Boot Code sequence. The SPI master electrical characteristics

are defined in SPI Master Characteristics and timing characteristics are defined in Figure 8. The TPS65982 is

designed to power the flash from LDO_3V3 to support dead-battery or no-battery conditions, and therefore pullup

resistors used for the flash memory must be tied to LDO_3V3. The flash memory IC must support 12 MHz SPI

clock frequency. The size of the flash must be at least 1 Mbyte (equivalent to 8 Mbit) to hold the standard

application code outlined in Application Code. The SPI master of the TPS65982 supports SPI Mode 0. For Mode

0, data delay is defined such that data is output on the same cycle as chip select (SPI_SSZ pin) becomes active.

The chip select polarity is active-low. The clock phase is defined such that data (on the SPI_MISO and

SPI_MOSI pins) is shifted out on the falling edge of the clock (SPI_CLK pin) and data is sampled on the rising

edge of the clock. The clock polarity for chip select is defined such that when data is not being transferred the

SPI_CLK pin is held (or idling) low. The minimum erasable sector size of the flash must be 4 kB. The W25Q80

flash memory IC is recommended. Refer to TPS65982 I2C Host Interface Specification for instructions for

interacting with the attached flash memory over SPI using the host interface of the TPS65982.

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