PCF8813 datasheet(31/72 Pages) PHILIPS

31 / 72 page

2004 Mar 05

Philips Semiconductors

Product speciﬁcation

(67 + 1)

× 102 pixels matrix LCD driver

PCF8813

Table 7

Read status byte

BIT

FUNCTION

BUSY

0 = chip is able to accept new commands; 1 = chip is unable to accept new commands

DON

0 = display OFF; 1 = display ON

RES

0 = reset NOT in progress; 1 = reset in progress

MF[2:0]

manufacturer identiﬁcation bits

DS[1:0]

device recognition; currently has a ﬁxed value of 00 (recognition bits for a driver with 64 to 67 rows)

Table 8

Display control; bits D and E

Table 9

Set temperature coefﬁcient; bits TC[1:0]

Table 10 Set voltage multiplication factor; bits S[1:0]

11.1

Initialization

Immediately following Power-on, all internal registers as

well as the RAM content are undefined. A RES pulse must

be applied to the reset input.

Reset is accomplished by applying an external reset pulse

(active LOW) at the pad RES. When reset occurs within

the specified time all internal registers are reset, however

the RAM is still undefined. The RES input must be

≤0.3VDD

when VDD reaches VDD(min) (or higher) within a maximum

time tVHRL after VDD going HIGH (see Fig.37).

A reset can also be made by sending a reset command.

This command can be used during normal operating but

not to initialize the chip after Power-on.

11.2

Reset function

After reset the LCD driver has the following state:

• Power-down mode (PD = 1)

• Horizontal addressing (V = 0)

• Normal instruction set (H = 0)

• Display blank (D andE=00)

• Address counter X[6:0] = 0000000 and Y[3:0] = 0000

• Temperature control mode TC[1:0] = 00

• VLCD is equal to 0 and PRS = 0

• Power control is enabled (PC = 1)

• Normal row driving of display (N/P=1)

• Partial mode set for all rows available

(M[7:0] = 11111111)

• HV generator programmed off (VPR[6:0] = 0000000)

• 2 × voltage multiplier (S[1:0] = 00)

• After power-on, RAM data is undefined, the reset signal

does not change the content of the RAM

• Data order DO = 0

• All LCD outputs at VSS (display off)

• Bias system (BS[2:0] = 000

• Display start line set to R0 (C[6:0] = 000000)

• RAM line address set to 0 (L[6:0] = 000000)

• Maximum X address = 101 (Xmax[6:0] = 1100101)

• Maximum Y address = 8 (Ymax[3:0] = 1000)

• Display is not mirrored (MX = 0; MY = 0 and BRS = 0).

11.3

Power-down mode

Power-down mode gives the following circuit status:

• VLCD discharges to VSS as Power-down mode occurs

• All LCD outputs go to VSS (display off)

• Bias generator and VLCD generator switch-off, VLCD can

be disconnected

• Oscillator switches off (external clock is possible)

• RAM contents are not cleared; RAM data can be written.

FUNCTION

display blank

normal mode

all display segments on

inverse video mode

TC1

TC0

FUNCTION

VLCD temperature coefﬁcient 0

VLCD temperature coefﬁcient 1

VLCD temperature coefﬁcient 2

VLCD temperature coefﬁcient 3

FUNCTION

× voltage multiplier

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