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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PCF8813 датащи(PDF) 41 Page - NXP Semiconductors |
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PCF8813 датащи(HTML) 41 Page - NXP Semiconductors |
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41 / 72 page  2004 Mar 05 41 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 3-line and 4-line SPI and serial interface; VDD1 = 1.8 to 3.3 V; Figs 41 to 44; note 5 fSCLK SCLK frequency −− 9 MHz Tcyc SCLK cycle time 111 −− ns tPWH1 SCLK pulse width HIGH 45 −− ns tPWL1 SCLK pulse width LOW 45 −− ns tPWH2 SCE minimum HIGH time 50 −− ns tS1 SDATA set-up time 50 −− ns tH1 SDATA hold time 50 −− ns tS2 SCE set-up time 60 −− ns tH2 SCE hold time 45 −− ns tS3 data/command set-up time 50 −− ns tH3 data/command hold time 50 −− ns t1 SDOUT access time −− 80 ns t2 SDOUT disable time note 6 −− 80 ns t3 SCE hold time 50 −− ns t4 SDOUT disable time note 7 −− 80 ns Cb capacitive load for SDOUT note 8 −− 30 pF Rb series resistance for SDOUT note 8 −− 500 Ω I2C-bus interface in Fast-mode; VDD1 = 1.7 to 3.3 V; Fig.45 fSCL SCL clock frequency 0 − 400 kHz tLOW SCL clock low period 1.3 −−µs tHIGH SCL clock high period 0.6 −−µs tSU;DAT data set-up time 100 −− ns tHD;DAT data hold time 0 − 0.9 µs cb capacitive load represented by each bus line −− 400 pF tSU;STA set-up time for a repeated START condition 0.6 −−µs tHD;STA START condition hold time 0.6 −−µs tSU;STO set-up time for STOP condition 0.6 −−µs tSP tolerable spike width on bus note 9 −− 50 ns I2C-bus interface in Hs-mode; VDD1 = 1.7 to 3.3 V; Fig.46 fSCLH SCLH clock frequency 0 − 3.4 MHz tSU;STA set-up time (repeated) START condition 160 - − ns tHD;STA hold time (repeated) START condition 160 −− ns tLOW LOW period of the SCLH clock 160 −− ns tHIGH HIGH period of the SCLH clock 60 −− ns tSU;DAT data set-up time 10 −− ns SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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