PCF8813 datasheet(40/72 Pages) PHILIPS

40 / 72 page

2004 Mar 05

Philips Semiconductors

Product speciﬁcation

(67 + 1)

× 102 pixels matrix LCD driver

PCF8813

8. VLCD external voltage applied to VLCDIN and VLCDSENSE inputs; VLCDOUT disconnected; VPR and PC set to 0 (charge

pump off); display load current is not transmitted to IDD.

9. Load current = 10

µA; outputs tested one at a time.

16 AC CHARACTERISTICS

VDD1 = 1.7 to 3.3 V; VSS =0V; VLCD = 3.0 to 9.0 V; Tamb = −40 to +85 °C; all timings speciﬁed are based on

20% to 80% of VDD with an input voltage swing of VSS to VDD; unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

fext

external clock frequency

note 1

kHz

fframe

frame frequency

internal oscillator

note 2

note 3

tVHRL

VDD on to RES LOW time

see Fig.37

0(4)

−

µs

tRW

reset pulse width LOW time

see Fig.37

500

−−

tR(oper)

end of reset pulse to interface

operational

see Fig.37

1000

−−

6800-type parallel bus; VDD1 = 1.8 to 3.3 V; see Figs 38 and 39

tDCSU

data/command set-up time

−

tDCHD

data/command hold time

−−

TDS(cyc)

data strobe cycle time

1000

−−

tDSL

data strobe LOW time

300

−−

tDSH

data strobe HIGH time

300

−−

tRWSU

read/write set-up time

−−

tRWHD

read/write hold time

−−

tESU

chip enable set-up time

−−

tEHD

chip enable hold time

−−

tDATSU

data set-up time

−−

tDATHD

data hold time

−−

tDATACC

output access time

−−

280

tDATOH

output disable time

−

200

8080-type parallel bus; VDD1 = 1.8 to 3.3 V; see Fig.40

tDCSU

data/command set-up time

−

tDCHD

data/command hold time

−−

TDS(cyc)

data strobe cycle time

1000

−−

tDSLR

data strobe LOW time (read)

120

−−

tDSLW

data strobe LOW time (write)

240

−−

tDSHR

data strobe HIGH time (read)

120

−−

tDSHW

data strobe HIGH time (write)

120

−−

tDATSU

data set-up time

−−

tDATHD

data hold time

−−

tDATACC

output access time

−−

280

tDATOH

output disable time

−

200

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