PCF8813 datasheet(20/72 Pages) PHILIPS

20 / 72 page

2004 Mar 05

Philips Semiconductors

Product speciﬁcation

(67 + 1)

× 102 pixels matrix LCD driver

PCF8813

9.2

Serial interface (3-line)

handbook, full pagewidth

MGW713

transmission byte

MSB

LSB

transmission byte (1)

D/C

transmission byte

D/C

transmission byte

D/C

Fig.20 Serial data stream, write mode.

(1) A transmission byte may be a command byte or a data byte.

The serial interface is also a 3-line bidirectional interface

for communication between the microcontroller and the

LCD driver chip. The three lines are: SCE (chip enable),

SCLK (serial clock) and SDATA (serial data). The

PCF8813 is connected to the SDA of the microcontroller

by the SDATA (data input) and SDOUT (data output) pads

which are connected together.

9.2.1

WRITE MODE

In the write mode of the interface, the microcontroller

writes commands and data to the PCF8813. Each data

packet contains a control bit D/C and a transmission byte.

If D/C is LOW, the following byte is interpreted as a

command byte. If D/C is HIGH, the following byte is stored

in the display data RAM. The address counter is

incremented automatically after every data byte. Figure 20

shows the general format of the write mode and the

definition of the transmission byte.

Any instruction can be sent in any order to the PCF8813.

The MSB of a byte is transmitted first. The serial interface

is initialized when SCE is HIGH. In this state, SCLK clock

pulses have no effect and no power is consumed by the

serial interface. A falling edge on SCE enables the serial

interface and indicates the start of data transmission.

Figures 21, 22 and 23 show the protocol of the write

mode:

• When SCE is HIGH, SCLK clocks are ignored; the serial

interface is initialized during the HIGH time of SCE (see

Fig.21)

• At the falling SCE edge SCLK must be LOW (see

Fig.41)

• SDATA is sampled at the rising edge of SCLK

• D/C indicates whether the byte is a command (D/C=0)

or RAM data (D/C = 1); it is sampled with the first rising

SCLK edge

• If SCE stays LOW after the last bit of a command/data

byte, the serial interface is ready for the D/C-bit of the

next byte at the next rising edge of SCLK (see Fig.22).

• A reset pulse with RES interrupts the transmission and

the data being written into the RAM may be corrupted.

The registers are cleared. If SCE is LOW after the rising

edge of RES, the serial interface is ready to receive the

D/C-bit of a command/data byte (see Fig.23).

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