PCF8813 datasheet(15/72 Pages) PHILIPS

15 / 72 page

2004 Mar 05

Philips Semiconductors

Product speciﬁcation

(67 + 1)

× 102 pixels matrix LCD driver

PCF8813

7.13

Bottom row swap

This mode swaps the order of the order of the rows; see

Figs 13 and 14. The mode is useful to aide routing to

displays when it is not possible to pass tracks under the

device, as in the case of Tape Carrier Packages (TCP).

7.14

Output row order

The order in which the rows are activated is a function of

bits Bottom Row Swap (BRS), Mirror Y (MY) and Normal

Partial mode (N/P). This has important implications when

the device is used either in COG or TCP applications.

When MY is set to 0, the RAM is accessed in a linear

manner, starting at R0, counting to R66, then jumping to

the end for the icon data. When MY is set to 1, the RAM is

still accessed in a linear manner but starting from the last

row, counting down to zero and then jumping to the icon

data.

When N/P is set to 1, the Free Programmable Mux Rate

(FPMR) mode is disabled and row addressing is in normal

mode (see Section 11.9), therefore counting is the same

as for MY = 0 and BRS = 0. When N/P is 0, FPMR mode

is enabled. Only 65 rows are addressed/read in FPMR

mode.

Figures 13 and 14 show the possibility of connecting the

icon row (row R67) at the top or bottom of the display.

handbook, full pagewidth

MGW793

INTERFACE

COLUMNS

R15

R16

RAM

R31

R32

R47

R48

R63

R67

R66

R67

Fig.13 Row order and interconnection with BRS = 0, MY = 0 and N/P=1.

PCF8813 датащи(PDF) 15 Page - NXP Semiconductors

PCF8813 датащи(HTML) 15 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

датащи скачать

ссылки URL