PCF8813 datasheet(6/72 Pages) PHILIPS

6 / 72 page

2004 Mar 05

Philips Semiconductors

Product speciﬁcation

(67 + 1)

× 102 pixels matrix LCD driver

PCF8813

Notes

1. Dummy pads are located at positions 1, 2, 3, 5, 6, 179, 180, 181, 182 and 274; dummy and alignment pads are

located at positions 4 and 178.

2. When not in use, this pad must be connected to VDD1 or VSS1.

3. Output SDAHOUT is used as the data acknowledge output when the I2C-bus is selected. By connecting SDAHOUT

to SDAH externally, the SDAH line becomes fully I2C-bus compatible. Having the acknowledge output separated

from the serial data line is advantageous in COG applications because where the track resistance from the

SDAHOUT pad to the SDAH line can be significant, a potential divider is generated by the bus pull-up resistor and

the ITO track resistance. Therefore it is possible during the acknowledge cycle that the PCF8813 will not create a

logic LOW level. By splitting the SDAH input from the SDAHOUT output, the device could be used in a mode that

ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to

minimize the track resistance from the SDAHOUT pad to the system SDAH line to guarantee a valid LOW level.

4. VDD2 and VDD3 supply the internal voltage generator, both have the same voltage and may be connected together

outside of the chip; VDD1 supplies the remainder of the chip. VDD1, VDD2 and VDD3 can be connected together but

then care must be taken with respect to the supply voltage range. If the internal voltage generator is not used, pads

VDD2 and VDD3 must be connected to pads VDD1.

5. This pad can be used to tie-off unused input pads to the power supply voltage or to ground.

6. This input is not used in serial and I2C-bus mode and must therefore be connected to either VDD1 or VSS1.

7. This input is not used when the serial or I2C-bus interface is selected and must therefore be connected to VDD1 or

VSS1.

8. When serial or I2C-bus mode is selected, the unused parallel pads must be connected to VDD1 or VSS1.

9. Supply rails VSS1 and VSS2 must be connected together.

10. This input is not used with the 3-line serial interface and must therefore be connected to VDD1 or VSS1.

11. This pad can be connected externally to the SCE/SCLH pad to reduce the number of pads routed in COG

applications. When not connected in this configuration, VOTPPROG must be connected to either VDD1 or VSS1 after

completion of OTP programming and after the seal bit has been set.

12. When the on-chip oscillator is used, the OSC input must be connected to VDD1. If an external clock signal is used,

then this is connected to the OSC input. If both the oscillator and external clock are inhibited by connecting pad OSC

to VSS1, the display is not clocked and may be in a DC state. To avoid this, the chip should always be put into

Power-down mode before stopping the clock.

13. Test pads T1 to T5 are not accessible to users: T1, T2 and T5 must be connected to VSS; T3 and T4 must be

open-circuit.

14. Positive power supply for the liquid crystal display (see also Figs 51, 52 and 53):

a) If the internal voltage generator is used, pads VLCDIN,VLCDSENSE and VLCDOUT must be connected together.

b) An external LCD supply voltage can be supplied using the VLCDIN pad, this requires that pad VLCDOUT is

open-circuit, pad VLCDSENSE is connected to the VLCDIN input, and the internal voltage generator is switched off.

In Power-down mode, the external LCD supply voltage must be switched off.

VLCDIN

256 to 262

LCD supply voltage input; note 14

VLCDOUT

263 to 271

generated LCD supply voltage; note 14

VLCDSENSE

272

voltage multiplier (VLCD) regulation input; note 14

RES

273

external reset input

SYMBOL

PAD(1)

DESCRIPTION

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