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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AXP288D датащи(PDF) 38 Page - Shenzhen X-Powers Technology Co ., Ltd |
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AXP288D датащи(HTML) 38 Page - Shenzhen X-Powers Technology Co ., Ltd |
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38 / 110 page  AXP288 PMIC Optimized For Multi-Core High-Performance System AXP288 Datasheet V1.06 Copyright © 2014 X-Powers Limited. All Rights Reserved. 38 BYT SoC initiated global reset PLTRST_B SLP_S0IX_B COREPWROK VCCAPWROK Buck2 - V1P0SX LDO1 - V1P2SX Non-default on rails LDO6 - eMMC Signals from SoC Buck1 - VCC T0 0 Power up triggered based on SLP_S0IX_B signal rising edge T1 SUSPWRDNACK Figure 9-13 Note: • Power down and power up timing follow cold off and cold boot timing • Rail power up sequencing will wait until SLP_S0IX_B signal goes high to begin the sequence • If SLP_S0IX_B signal goes high before power down sequence completes, power down sequence should complete before power up begins • PLTRST_B to SLP_S0IX_B delay could be zero Table 9-12 Parameter Description Min Typical Max Units T0 Time that the SLP_S0IX_B signal stays low 0.1 No max ms T1 Time for which rails stay down before power up sequence begins 50 ms |
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