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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AXP288D датащи(PDF) 36 Page - Shenzhen X-Powers Technology Co ., Ltd |
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AXP288D датащи(HTML) 36 Page - Shenzhen X-Powers Technology Co ., Ltd |
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36 / 110 page  AXP288 PMIC Optimized For Multi-Core High-Performance System AXP288 Datasheet V1.06 Copyright © 2014 X-Powers Limited. All Rights Reserved. 36 Parameter Description Min Typical Max Units T3 VCCAPWROK and COREPWROK de-assertion to first VR starts to turn off 0 150 μs T4 Rail Ramp-down Time from 90% to 10% voltage level 0.5 1 2 ms T5 Rail to Subsequent Rail Turn-Off Delay 0.5 1 3 ms T6 DRAMPWROK de-assertion to RSMRST_B assertion 150 μs 9.1.4 Cold Reset and Global reset Reset types: • Global reset: partial power down followed by power up • Cold reset: full power down followed by power up There are two special scenarios where a cold reset can be enabled by having the SoC either initiate a cold off or a cold reset in conjunction with a bit in the PMIC being set. These two bits are the COLDRSTEN1 and COLDRSTEN bits as defined below. Table 9-9 BIT NAME FUNCTION DEFAULT D[7:2] RSVD Reserved 0 D[1] COLDRSTEN1 Sets whether a global reset or cold reset is done when a global reset is initiated by the SoC 0 – COLD RESET not enabled 1 – COLD RESET enabled 0 D[0] COLDRSTEN Sets whether a cold off or cold reset is done when a cold off is initiated by the SoC 0 – COLD RESET not enabled 1 – COLD RESET enabled 0 Cold Reset scenario 1: The diagram below shows the first special case of a cold reset being enabled based on a cold off and the PMIC register bit being set. |
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