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AXP288D датащи(PDF) 27 Page - Shenzhen X-Powers Technology Co ., Ltd

номер детали AXP288D
подробное описание детали  PMIC Optimized For Multi-Core High-Performance System
PDF  110 Pages
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AXP288D датащи(HTML) 27 Page - Shenzhen X-Powers Technology Co ., Ltd

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AXP288
PMIC Optimized For Multi-Core High-Performance System
AXP288 Datasheet V1.06
Copyright © 2014 X-Powers Limited. All Rights Reserved.
27
Parameter
Description
Min
Typical
Max
Units
T2
V3P3A valid to RSMRST_B
de-assertion
0
150
μs
T3
VREFDQ valid (within +/-10% of
its final normal value) to
DRAMPWROK assertion
0
150
μs
T4
RSMRST_B
de-assertion
toSLP_S0IX_B de-assertion
80
μs
T5
SLP_S0IX_B de-assertion to first
SX rail turn-on delay
0
8
16
ms
T6
Core rails valid to VCCAPWEROK
and COREPWROK assertion
1
ms
T7
COREPWROK
assertion
to
PLTRST_B de-assertion
60
μs
VBAT
VRTC
Buck3-
V1P05S/V1P0A/V1P0S
Buck6-V3P3A&ELDO1-
V1P8A
LDO2-V1P2A/S
LDO3-V3P3A
RSMRST_B
SUSPWRDNACK
Buck4-VDDQ
LDO5-VREFDQ
DRAMPWROK
Buck5 - VNN
Buck1-VCC
LDO6-eMMC
SLP_S0IX_B
LDO1-V1P2SX
Buck2-V1P0SX
VCCAPWROK
COREPWROK
PLTRST_B
Signals from SoC
BYT Cold Boot Sequence for AXP288D
0
T0
T1
T2
T3
T4
T5
T6
T7
Figure 9-6



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