AXP288D datasheet(59/110 Pages) XPOWER

59 / 110 page

AXP288

PMIC Optimized For Multi-Core High-Performance System

AXP288 Datasheet V1.06

9.8 Interrupt Controller

PMIC Interrupt Controller monitors such as low power, bad battery, PWRON pin signal, over temperature, GPIO input

edge signals such as trigger events. When the events occur, corresponding IRQ status will be set to 1, and will drive IRQ pin

(NMOS open drain) asserted low. When host detect triggered IRQ signal, host will scan through the trigger events and respond

accordingly. Meanwhile, Host will reset the IRQ status by writing “1” to status bit. Host will always check every IRQ status from

time to time and only will take effect with respective relevant enabled IRQ bit only.

The input edge IRQ of GPIO will only functions when GPIO pin is set as Digital input, and the function will take effect when

input edge IRQ is enable . The input will go through about 1ms of de-bounce and corresponding IRQ will trigger when detect

rising and falling edge. Rising, falling, or both edge triggering is control by corresponding IRQ register bit.

8bits event timer will issue timeout IRQ. Clearing IRQ doesn’t start counter.

9.9 TWSI

The PMIC is compatible with a host-controlled environment, functioned as a slave port enabling serial interface

compatible hosts to write to or read from internal registers. The PMIC only responds (ACK) to address 68H/69H.

Table 9-46

BYTE

BIT

MSB

WRITE

READ

I/O DATA BUS

Incremental Read:

The PMIC support incremental read operations in normal TWI mode. The address increases by 1 automatically.

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