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AXP288D датащи(PDF) 26 Page - Shenzhen X-Powers Technology Co ., Ltd

номер детали AXP288D
подробное описание детали  PMIC Optimized For Multi-Core High-Performance System
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AXP288
PMIC Optimized For Multi-Core High-Performance System
AXP288 Datasheet V1.06
Copyright © 2014 X-Powers Limited. All Rights Reserved.
26
9.1.2 Power up sequence
Specially for Intel mode:
Buck3 - V1P05S/V1P0A/
V1P0S
Buck6 - V1P8
LDO2 - V1P2A/S
LD03 -V3P3A
RSMRST_B
LDO5 - VREFDQ
DRAMPWROK
BYT Cold Boot Sequence
Buck1 - VCC
Buck4 - VDDQ
LDO 6 - eMMC
LDO1 - V1P2SX
Buck2 - V1P0SX
VCCAPWROK
COREPWROK
VBAT
VRTC
SUSPWRDNACK
SLP_S0IX_B
PLTRST_B
Signals from SoC
T0
T1
T2
T3
T5
T6
T7
Buck5 - VNN
T4
0
Figure 9-5
Note:
•
Buck 3, 5 and 6 power up at the same time
•
PMIC Power up sequence has no dependency on SUSPWRDNAK signal
•
SLP_S0IX_B signal gates pmic performing the remainder power up sequence
Table 9-2
Parameter
Description
Min
Typical
Max
Units
T0
Rail Ramp-Up Time from 10% to
90% voltage level
0.08
1
2
ms
T1
Rail to Subsequent Rail Turn-On
Delay
0.5
1
2.05
ms



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