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AXP288D датащи(PDF) 67 Page - Shenzhen X-Powers Technology Co ., Ltd

номер детали AXP288D
подробное описание детали  PMIC Optimized For Multi-Core High-Performance System
PDF  110 Pages
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AXP288D датащи(HTML) 67 Page - Shenzhen X-Powers Technology Co ., Ltd

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AXP288
PMIC Optimized For Multi-Core High-Performance System
AXP288 Datasheet V1.06
Copyright © 2014 X-Powers Limited. All Rights Reserved.
67
4
Select the BUCK2/ 3 /5 Vrun register or Vsleep register
0:Vrun Register
1:Vsleep Register
RW
0
3
If SLP_S0IX_B go high and PLTRST_B status is low for 512ms, PMIC will do a cold reset
or not (Reset: power on reset)
0: don't cold reset
1: do a cold reset
RW
1
2
Cold reset Enable set bit
0:Disable
1:Enable
All power rails power down and then power up,64ms delay
RW
0
1
Power control register select
1-select buffer register, output value of
control register to buffer
0-select the control register
RW
0
0
Output buffer register value
1-outport to control register from buffer
Bit[1:0], self clear to 0 after output
RW
0
REG 15H: DLDO1 voltage control
Default：16H
Reset: System reset
Table 10-10
Bit
Description
R/W
Default
7-5
Reserved
RW
000
4-0
voltage setting Bit 4-0, default is 2.9V
0.7V-3.3V, 100mV/step
RW
16H
REG 16H: DLDO2 voltage control
Default：16H
Reset: System reset
Table 10-11
Bit
Description
R/W
Default
7-5
Reserved
RW
000
4-0
voltage setting Bit 4-0, default is 2.9V
0.7V-3.4V, 100mV/step
RW
10110



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