AD6636BBCZ1 datasheet(25/72 Pages) AD

25 / 72 page

AD6636

Rev. 0 | Page 25 of 72

Table 11. Correction Control Registers

Bits

Decription

I/Q Correction Control

15–12

Amplitude Loop BW

11–8

Phase Loop BW

7–4

DC Loop BW

Reserved (Logic 0)

Amplitude Correction

Enable

Phase Correction Enable

DC Correction Enable

DC Offset Correction I

31–16

DC Offset Q

DC Offset Correction Q

15–0

DC Offset I

Amplitude Offset

Correction

31–16

Amplitude Correction

Phase Offset Correction

15–0

Phase Correction

DC Correction

All ADCs have a nominal dc offset related to them. If the ADCs

in the I and Q path have different dc offsets due to variations in

manufacturing process, the dc correction circuit can be used to

compensate for these dc offsets. Writing Logic 1 into the dc

correction enable bit of the AB (or CD) correction control

blocks are used, one each for the I and Q paths. The estimated

dc value is subtracted from the I and Q paths. Therefore, the dc

signal is removed independently from the I and Q path signals.

A cascade of two low-pass decimating filters estimates the dc

offset in the feedback loop. A decimating first-order CIC filter is

followed by an interpolating second-order CIC filter. The

decimation and interpolation values of the CIC filters are the

same and are programmable between 212 and 224 in powers of 2.

The 4-bit dc loop BW word in the I/Q correction control AB (or

CD) register is used to program this decimation (interpolation)

value. When the dc loop BW is a 0, decimation is 212, and when

the dc loop BW is 11, decimation is 224.

When the dc correction circuit is enabled, the dc correction

values are estimated. The values, which are estimated independ-

ently in the I and Q paths, are subtracted independently from

their respective datapaths. These dc correction values are also

available for output continuously through the dc correction I

and dc correction Q registers. These registers contain register

16-bit dc offset values whose MSB-justified values are

subtracted directly from MSB-justified ADC inputs for the I

and Q paths.

When the dc correction circuit is disabled, the value in the dc

correction register is used for continuously subtracting the dc

offset from I and Q datapaths. This method can be used to

manually set the dc offset instead of using the automatic dc

correction circuit.

Phase Correction

When using complex ADC input, the I and Q datapaths

typically have phase offset, caused mainly by the local oscillator

and demodulator IC. The AD6636 phase-offset correction

circuit can be used to compensate for this phase offset.

When the phase correction enable bit is Logic 1, the phase error

between I and Q is estimated (ideally, the phase should be 90°).

The phase mismatch is estimated over a period of time

determined by the integrator loop bandwidth. This integrator is

implemented as a first-order CIC decimating filter, whose

decimation value can vary between 212 and 224 in powers of 2.

Phase loop BW (Bits [11:8]) of the I/Q correction control

equals 0, the decimation value is 212, and when phase loop BW is

11, the decimation value is 224.

While the phase offset correction circuit is enabled, the

tan(phase_mismatch) is estimated continuously. This value is

multiplied with Q path data and added to I path data

continuously. The estimated value is also updated in the phase

offset correction register. The tan(phase_mismatch) can be

±0.125 with a 14-bit resolution. This converts to a phase

mismatch of about ±7.125°.

When the phase offset correction circuit is disabled, the value in

the phase correction register multiplied with the Q path data

and added to the I path data continuously. This method can be

used to manually set the phase offset instead of using the

automatic phase offset correction circuit.

Amplitude Correction

When using complex ADC input, the I and Q datapaths

typically have amplitude offset, caused mainly by the local

oscillator and the demodulator IC. The AD6636 amplitude

offset correction circuit can be used to compensate for this

amplitude offset.

When the amplitude correction enable bit is Logic 1, the

amplitude error between the I and Q datapaths is estimated. The

amplitude mismatch is estimated over a period of time

determined by the integrator loop bandwidth. This integrator is

implemented as a first-order CIC decimating filter, whose

decimation value can vary between 212 and 224 in powers of 2.

Phase loop BW (Bits [11:8]) of the I/Q correction control

BW equals 0, the decimation value is 212, and when phase loop

BW is 11, the decimation value is 224.

While the amplitude offset correction circuit is enabled, the

difference (MAG(Q) – MAG(I)) is estimated continuously. This

value is multiplied with the Q path data and added to the Q

path data continuously. The estimated value is also updated in

the phase offset correction register. The difference (MAG(Q) –

MAG(I)) can be between 1.125 and 0.875 with a 14-bit

resolution.

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