AD6636BBCZ1 datasheet(71/72 Pages) AD

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AD6636

Rev. 0 | Page 71 of 72

If JTAG is used, the designer should ensure that the TRST

pin is pulled low during power-up. After the power

supplies have settled to nominal values (1.8 V and 3.3 V),

the TRST pin can be pulled high for JTAG control. When

JTAG control is no longer required, the TRST pin should

ideally be pulled low again.

• The CPUCLK (SCLK) is the clock used for programming

via the microport (serial port). This clock needs to be

provided by the designer to the part (slave clock). The

designer should ensure that this clock’s frequency is less

than or equal to the frequency of the CLKA signal.

Additionally, the frequency of the CPUCLK (SCLK) should

always be less than 100 MHz.

• CLKA, CLKB, CLKC, and CLKD are used as individual

clocks to input data into Input Ports A, B, C, and D,

respectively. All these clocks are required to have same

frequency and should ideally be generated from the same

clock source. Note that CLKA is used to drive the internal

circuitry and the PLL clock multiplier. Therefore, even if

Input Port A is not used, CLKA should be driven by the

input clock.

• The microport data bus is 16 bits wide. Both 8-bit and 16 bit

modes are available using this part. If 8-bit mode is used, the

MSB of the data bus (D[15:8]) can be left floating or

connected to GND.

• The output parallel port has a one clock cycle overhead. If

two channels (with the same data rates) are output on one

output port in 16-bit interleaved I/Q mode along with an

AGC word, this requires three clock cycles for one sample

from each channel (one clock each for I data, Q data, and

gain data). Therefore, the total number of clock cycles

required to output the data is 3 clocks/channel × 2 channels

+ 1 (overhead) = 7 clock cycles.

The number of clock cycles required for each channel can

be 3 (interleaved I + Q + gain word), or 2 (parallel I /Q +

gain) or 2 (interleaved I + Q) or 1 (interleaved I/Q).

Designers should make sure that sufficient time is allowed

to output these channels on one output port. Also note that

the I, Q, and gain for a particular channel all come out on a

single output port and cannot be divided among output

ports.

• When CRCF and DRCF filters are disabled, the coefficient

memory cannot be read back, because the clock to the

coefficient RAM is also cut off.

• In the Intel mode microport, the beginning of a read and

write access is indicated by the RDY pin going low. The

access is complete only when the RDY pin goes high. In the

Motorola mode microport, the completion of a read and

write access is indicated by the DTACK going low. In both

modes, CS, RD (DS), and WR (R/W) should be active until

access is complete; otherwise, an incomplete access results.

• In both Intel and Motorola modes, if CS is held low even

after microport read or write access is complete, the

microport initiates a second access. This is a problem while

writing or reading from coefficient RAM, where each access

writes to or reads from a different RAM address. This can be

fixed by writing to one coefficient RAM address at a time,

that is, the coefficient start and stop address registers have

the same value.

• In SPI mode programming, the SCS pin needs to go high

(inactive) after writing or reading each byte (eight clock

cycles on the SCLK pin).

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